def mult_t_base(self, len_a, len_b):
a, b, reset = pyrtl.Input(len_a, "a"), pyrtl.Input(len_b,
"b"), pyrtl.Input(
1, 'reset')
product, done = pyrtl.Output(name="product"), pyrtl.Output(name="done")
m_prod, m_done = multipliers.simple_mult(a, b, reset)
product <<= m_prod
done <<= m_done
self.assertEqual(len(product), len_a + len_b)
xvals = [int(random.uniform(0, 2**len_a - 1)) for i in range(20)]
yvals = [int(random.uniform(0, 2**len_b - 1)) for i in range(20)]
true_result = [i * j for i, j in zip(xvals, yvals)]
mult_results = []
for x_val, y_val, true_res in zip(xvals, yvals, true_result):
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
sim.step({a: x_val, b: y_val, reset: 1})
for cycle in range(len(a) + 1):
sim.step({a: 0, b: 0, reset: 0})
# Extracting the values and verifying correctness
mult_results.append(sim.inspect("product"))
self.assertEqual(sim.inspect("done"), 1)
self.assertEqual(mult_results, true_result)
def mult_t_base(self, len_a, len_b, shifts):
a, b = pyrtl.Input(len_a, 'a'), pyrtl.Input(len_b, 'b')
reset = pyrtl.Input(1, 'reset')
product, done = pyrtl.Output(name='product'), pyrtl.Output(name='done')
m_prod, m_done = multipliers.complex_mult(a, b, shifts, reset)
product <<= m_prod
done <<= m_done
self.assertEqual(len(product), len_a + len_b)
xvals = [int(random.uniform(0, 2**len_a - 1)) for i in range(20)]
yvals = [int(random.uniform(0, 2**len_b - 1)) for i in range(20)]
true_result = [i * j for i, j in zip(xvals, yvals)]
mult_results = []
for x_val, y_val, true_res in zip(xvals, yvals, true_result):
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
sim.step({a: x_val, b: y_val, reset: 1})
if shifts <= len_a:
length = len_a // shifts + (1 if len_a % shifts == 0 else 2)
else:
length = len_a + 1
for cycle in range(length):
sim.step({a: 0, b: 0, reset: 0})
# Extracting the values and verifying correctness
mult_results.append(sim.inspect('product'))
self.assertEqual(sim.inspect('done'), 1)
self.assertEqual(mult_results, true_result)
def test_trace_to_html_repr_per_name_enum_is_bool(self):
from enum import IntEnum
class Foo(IntEnum):
A = 0
B = 1
i = pyrtl.Input(2, 'i')
state = pyrtl.Register(max(Foo).bit_length(), name='state')
o = pyrtl.Output(name='o')
o <<= state
with pyrtl.conditional_assignment:
with i == 0b01:
state.next |= Foo.A
with i == 0b10:
state.next |= Foo.B
sim = pyrtl.Simulation()
sim.step_multiple({'i': [1, 2, 1, 2, 2]})
htmlstring = pyrtl.trace_to_html(sim.tracer,
repr_per_name={'state': Foo})
expected = (
'<script type="WaveDrom">\n'
'{\n'
' signal : [\n'
' { name: "i", wave: "====.", data: ["0x1", "0x2", "0x1", "0x2"] },\n'
' { name: "o", wave: "0.101" },\n'
' { name: "state", wave: "=.===", data: ["Foo.A", "Foo.B", "Foo.A", "Foo.B"] },\n'
' ],\n'
' config: { hscale: 2 }\n'
'}\n'
'</script>\n')
self.assertEqual(htmlstring, expected)
def test_read_memindexed_ior(self):
self.mem = pyrtl.MemBlock(8, 8)
self.mem_val_map = {self.mem: {0: 5, 1: 4, 2: 3, 3: 2, 4: 1, 5: 0}}
decide = pyrtl.Input(1)
ind = pyrtl.Input(3)
x = self.mem[ind]
y = pyrtl.Output(8, 'y')
z = pyrtl.Output(8, 'z')
w = pyrtl.Output(8, 'w')
with pyrtl.conditional_assignment:
with decide:
y |= x
z |= x
with pyrtl.otherwise:
w |= x
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace,
memory_value_map=self.mem_val_map)
for i in range(5):
sim.step({decide: i % 2, ind: i})
if i == 0:
y_exp, z_exp, w_exp = 0, 0, 5
elif i == 1:
y_exp, z_exp, w_exp = 4, 4, 0
elif i == 2:
y_exp, z_exp, w_exp = 0, 0, 3
elif i == 3:
y_exp, z_exp, w_exp = 2, 2, 0
else:
y_exp, z_exp, w_exp = 0, 0, 1
self.assertEqual(sim.inspect(y), y_exp)
self.assertEqual(sim.inspect(z), z_exp)
self.assertEqual(sim.inspect(w), w_exp)
self.assertEqual(self.mem.num_read_ports, 1)
def test_two_way_concat(self):
i = pyrtl.Const(0b1100)
j = pyrtl.Const(0b011, bitwidth=3)
k = pyrtl.Const(0b100110)
o = pyrtl.Output(13, 'o')
o <<= pyrtl.concat(i, j, k)
block = pyrtl.working_block()
concat_nets = list(block.logic_subset(op='c'))
self.assertEqual(len(concat_nets), 1)
self.assertEqual(concat_nets[0].args, (i, j, k))
pyrtl.two_way_concat()
concat_nets = list(block.logic_subset(op='c'))
self.assertEqual(len(concat_nets), 2)
upper_concat = next(n for n in concat_nets if i is n.args[0])
lower_concat = next(n for n in concat_nets if k is n.args[1])
self.assertNotEqual(upper_concat, lower_concat)
self.assertEqual(upper_concat.args, (i, j))
self.assertEqual(lower_concat.args, (upper_concat.dests[0], k))
sim = pyrtl.Simulation()
sim.step({})
self.assertEqual(sim.inspect('o'), 0b1100011100110)
def test_blif_input_simulates_correctly_with_merged_outputs(self):
# The 'counter_blif' string contains a model of a standard 4-bit synchronous-reset
# counter with enable. In particular, the model has 4 1-bit outputs named "count[0]",
# "count[1]", "count[2]", and "count[3]". The internal PyRTL representation will by
# default convert these related 1-bit wires into a single 4-bit wire called "count".
# This test simulates the design and, among other things, ensures that this output
# wire conversion occurred correctly.
pyrtl.input_from_blif(counter4bit_blif)
io_vectors = pyrtl.working_block().wirevector_subset(
(pyrtl.Input, pyrtl.Output))
sim_trace = pyrtl.SimulationTrace(wires_to_track=io_vectors)
sim = pyrtl.Simulation(sim_trace)
inputs = {
'rst': [1] + [0] * 20,
'en': [1] + [1] * 20,
}
expected = {'count': [0] + list(range(0, 16)) + list(range(0, 4))}
sim.step_multiple(inputs, expected)
correct_output = (
" --- Values in base 10 ---\n"
"count 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3\n"
"en 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1\n"
"rst 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0\n"
)
output = six.StringIO()
sim_trace.print_trace(output)
self.assertEqual(output.getvalue(), correct_output)
def test_prng_xoroshiro128(self):
seed = pyrtl.Input(128, 'seed')
load, req = pyrtl.Input(1, 'load'), pyrtl.Input(1, 'req')
ready = pyrtl.Output(1, 'ready')
rand = pyrtl.Output(128, 'rand')
ready_out, rand_out = prngs.prng_xoroshiro128(128, load, req, seed)
ready <<= ready_out
rand <<= rand_out
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
in_vals = [random.randrange(1, 2**128) for i in range(5)]
for trial in range(5):
true_val = 0
for word in islice(TestPrngs.xoroshiro128plus(in_vals[trial]), 2):
true_val = true_val << 64 | word
sim.step({'load': 1, 'req': 0, 'seed': in_vals[trial]})
sim.step({'load': 0, 'req': 1, 'seed': 0x0})
for cycle in range(2, 4):
sim.step({'load': 0, 'req': 0, 'seed': 0x0})
circuit_out = sim.inspect(rand)
self.assertEqual(
circuit_out, true_val,
"\nAssertion failed on trial {}\nExpected value: {}\nGotten value: {}"
.format(trial, hex(true_val), hex(circuit_out)))
for ready_signal in sim_trace.trace['ready'][:3]:
self.assertEqual(ready_signal, 0)
self.assertEqual(sim_trace.trace['ready'][3], 1)
self.assertEqual(sim_trace.trace['ready'][4], 0)
def test_wallace_tree_1(self):
"""
Arithmatic tester version 2015.05
"""
# Creating the logic nets
a, b = pyrtl.Input(13, "a"), pyrtl.Input(14, "b")
product = pyrtl.Output(27, "product")
product <<= multipliers.tree_multiplier(a, b)
# creating the testing values and the correct results
xvals = [int(random.uniform(0, 2**13-1)) for i in range(20)]
yvals = [int(random.uniform(0, 2**14-1)) for i in range(20)]
true_result = [i * j for i, j in zip(xvals, yvals)]
# Setting up and running the tests
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(len(xvals)):
sim.step({a: xvals[cycle], b: yvals[cycle]})
# Extracting the values and verifying correctness
multiplier_result = sim_trace.trace[product]
self.assertEqual(multiplier_result, true_result)
# now executing the same test using FastSim
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.FastSimulation(tracer=sim_trace)
for cycle in range(len(xvals)):
sim.step({a: xvals[cycle], b: yvals[cycle]})
multiplier_result = sim_trace.trace[product]
self.assertEqual(multiplier_result, true_result)
def test_one_bit_adder_matches_expected(self):
temp1 = pyrtl.WireVector(bitwidth=1, name='temp1')
temp2 = pyrtl.WireVector()
a, b, c = pyrtl.Input(1, 'a'), pyrtl.Input(1, 'b'), pyrtl.Input(1, 'c')
sum, carry_out = pyrtl.Output(1, 'sum'), pyrtl.Output(1, 'carry_out')
sum <<= a ^ b ^ c
temp1 <<= a & b # connect the result of a & b to the pre-allocated wirevector
temp2 <<= a & c
temp3 = b & c # temp3 IS the result of b & c (this is the first mention of temp3)
carry_out <<= temp1 | temp2 | temp3
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(15):
sim.step({
'a': random.choice([0, 1]),
'b': random.choice([0, 1]),
'c': random.choice([0, 1])
})
htmlstring = inputoutput.trace_to_html(
sim_trace) # tests if it compiles or not
def step_with_bundle(self, obj):
w = pyrtl.Bundle(obj, "inst")
# funct7 rs2 rs1 funct3 rd opcode
# 0b 0000010 01100 01010 000 01011 0010011
w <<= 0b00000100110001010000010110010011
r = pyrtl.Register(len(w))
f7 = r.as_bundle(obj).funct7
r.next <<= w
y = r.as_bundle(obj)
sim = pyrtl.Simulation()
sim.step({})
assert sim.inspect(w.funct7) == 0b0000010
assert sim.inspect(w.rs2) == 0b01100
assert sim.inspect(w.rs1) == 0b01010
assert sim.inspect(w.funct3) == 0b000
assert sim.inspect(w.rd) == 0b01011
assert sim.inspect(w.opcode) == 0b0010011
assert sim.inspect(r) == 0
sim.step({})
assert sim.inspect(r) == 0b00000100110001010000010110010011
assert sim.inspect(f7) == 0b0000010
assert sim.inspect(y.funct7) == 0b0000010
assert sim.inspect(y.rs2) == 0b01100
assert sim.inspect(y.rs1) == 0b01010
assert sim.inspect(y.funct3) == 0b000
assert sim.inspect(y.rd) == 0b01011
assert sim.inspect(y.opcode) == 0b0010011
def mult_t_base(self, len_a, len_b, **mult_args):
# Creating the logic nets
a, b = pyrtl.Input(len_a, "a"), pyrtl.Input(len_b, "b")
product = pyrtl.Output(name="product")
product <<= multipliers.signed_tree_multiplier(a, b, **mult_args)
self.assertEqual(len(product), len_a + len_b)
# creating the testing values and the correct results
bound_a = 2**(len_a - 1) - 1
bound_b = 2**(len_b - 1) - 1
xvals = [int(random.uniform(-bound_a, bound_a)) for i in range(20)]
yvals = [int(random.uniform(-bound_b, bound_b)) for i in range(20)]
true_result = [i * j for i, j in zip(xvals, yvals)]
# Setting up and running the tests
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(len(xvals)):
sim.step({
a: libutils.twos_comp_repr(xvals[cycle], len_a),
b: libutils.twos_comp_repr(yvals[cycle], len_b)
})
# Extracting the values and verifying correctness
multiplier_result = [
libutils.rev_twos_comp_repr(p, len(product))
for p in sim_trace.trace[product.name]
]
self.assertEqual(multiplier_result, true_result)
def test_twos_comp_sim(self):
self.out <<= self.in1 + self.in2
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for i in range(10):
sim.step({'in1': i, 'in2': libutils.twos_comp_repr(-2 * i, 8)})
self.assertEquals(
-i, libutils.rev_twos_comp_repr(sim.inspect('out'), 8))
def check_trace(self, correct_string):
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for i in range(8):
sim.step({})
output = io.StringIO()
sim_trace.print_trace(output, compact=True)
self.assertEqual(output.getvalue(), correct_string)
def check_trace(self, correct_string):
sim = pyrtl.Simulation()
output_list = []
for i in range(8):
sim.step({})
output_list.append(sim.value[self.o])
bw = len(self.o)
spaced_output = ' '.join(str(pyrtl.val_to_signed_integer(x, bw)) for x in output_list)
self.assertEqual(spaced_output, correct_string)
def check_trace(self, correct_string):
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for i in range(8):
sim.step({})
output = six.StringIO()
sim_trace.print_trace(output, compact=True)
spaced_output = ' '.join(output.getvalue()) # add spaces to string
self.assertEqual(spaced_output, correct_string)
def test_assert_simulation(self):
i = pyrtl.Input(1)
o = pyrtl.rtl_assert(i, self.RTLSampleException('test assertion failed'))
sim = pyrtl.Simulation()
sim.step({i: 1})
self.assertEquals(sim.inspect(o), 1)
with self.assertRaises(self.RTLSampleException):
sim.step({i: 0})
def init_sim(testname):
file = open("tests/{}.s".format(testname), 'r')
enc_asm = file.readlines()[0][1:].strip()
asm = loads(b64decode(enc_asm).decode("UTF-8"))
i_mem_init = {int(k): v for k, v in asm.items()}
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace, memory_value_map={
i_mem : i_mem_init
})
return sim, sim_trace
def test_single_mul(self):
ina, inb = pyrtl.Input(bitwidth=4, name='a'), pyrtl.Input(bitwidth=4, name='b')
self.output <<= ina * inb
pyrtl.synthesize()
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for a in range(16):
for b in range(16):
sim.step({'a': a, 'b': b})
result = sim_trace.trace['r']
self.assertEqual(result, [a * b for a in range(16) for b in range(16)])
def check_op(self, op):
ina, inb = pyrtl.Input(bitwidth=4, name='a'), pyrtl.Input(bitwidth=4, name='b')
self.output <<= op(ina, inb)
pyrtl.synthesize()
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
for a in range(16):
for b in range(16):
sim.step({'a': a, 'b': b})
result = sim_trace.trace['r']
self.assertEqual(result, [op(a, b) for a in range(16) for b in range(16)])
def test_synthesize_merged_io_simulates_correctly(self):
pyrtl.synthesize()
sim = pyrtl.Simulation()
sim.step_multiple({
'a': [4, 6, 2, 3],
'b': [2, 9, 11, 4],
})
output = six.StringIO()
sim.tracer.print_trace(output, compact=True)
self.assertEqual(output.getvalue(), 'a 4623\n'
'b 29114\n'
'o 615137\n')
def test_verilog_testbench_does_not_throw_error(self):
zero = pyrtl.Input(1, 'zero')
counter_output = pyrtl.Output(3, 'counter_output')
counter = pyrtl.Register(3, 'counter')
counter.next <<= pyrtl.mux(zero, counter + 1, 0)
counter_output <<= counter
sim_trace = pyrtl.SimulationTrace([counter_output, zero])
sim = pyrtl.Simulation(tracer=sim_trace)
for cycle in range(15):
sim.step({zero: random.choice([0, 0, 0, 1])})
with io.StringIO() as tbfile:
pyrtl.output_verilog_testbench(tbfile, sim_trace)
def test_csprng_trivium(self):
"""
Trivium test vectors retrived from:
https://www.sheffield.ac.uk/polopoly_fs/1.12164!/file/eSCARGOt_full_datasheet_v1.3.pdf
bit ordering is modified to adapt to the Pyrtl implementation
"""
in_vector = pyrtl.Input(160, 'in_vector')
load, req = pyrtl.Input(1, 'load'), pyrtl.Input(1, 'req')
ready = pyrtl.Output(1, 'ready')
out_vector = pyrtl.Output(128, 'out_vector')
ready_out, rand_out = prngs.csprng_trivium(128, load, req, in_vector)
ready <<= ready_out
out_vector <<= rand_out
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
in_vals = [
0x0100000000000000000000000000000000000000,
0x0a09080706050403020100000000000000000000,
0xfffefdfcfbfaf9f8f7f600000000000000000000,
0xfaa75401ae5b08b5620fc760f9922bc45df68f28,
0xf5a24ffca95603b05d0abe57f08922bb54ed861f,
]
true_vals = [
0x1cd761ffceb05e39f5b18f5c22042ab0,
0x372e6b86524afa71b5fee86d5cebb07d,
0xc100baca274287277ff49b9fb512af1c,
0xcb5996fcff373a953fc169e899e02f46,
0xf142d1df4b36c7652cba2e4a22ee51a0,
]
for trial in range(5):
sim.step({'load': 1, 'req': 0, 'in_vector': in_vals[trial]})
for cycle in range(1, 20):
sim.step({'load': 0, 'req': 0, 'in_vector': 0x0})
sim.step({'load': 0, 'req': 1, 'in_vector': 0x0})
for cycle in range(21, 23):
sim.step({'load': 0, 'req': 0, 'in_vector': 0x0})
circuit_out = sim.inspect(out_vector)
self.assertEqual(
circuit_out, true_vals[trial],
"\nAssertion failed on trial {}\nExpected value: {}\nGotten value: {}"
.format(trial, hex(true_vals[trial]), hex(circuit_out)))
for ready_signal in sim_trace.trace['ready'][:19]:
self.assertEqual(ready_signal, 0)
self.assertEqual(sim_trace.trace['ready'][19], 1)
for ready_signal in sim_trace.trace['ready'][20:22]:
self.assertEqual(ready_signal, 0)
self.assertEqual(sim_trace.trace['ready'][22], 1)
self.assertEqual(sim_trace.trace['ready'][23], 0)
def simulate_circuit(circuit_inputs, input_bits, circuit_outputs):
"""
Simulate and record the circuit output by passing in `input_bits`.
"""
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
output_bits = []
for bits in input_bits:
bits_in = {inp.name: bit for inp, bit in zip(circuit_inputs, bits)}
sim.step(bits_in)
output_bits.append([sim.inspect(out) for out in circuit_outputs])
return output_bits
def test_aes_state_machine(self):
# self.longMessage = True
aes_key = pyrtl.Input(bitwidth=128, name='aes_key')
reset = pyrtl.Input(1)
ready = pyrtl.Output(1, name='ready')
encrypt_ready, encrypt_out = self.aes_encrypt.encrypt_state_m(
self.in_vector, aes_key, reset)
self.out_vector <<= encrypt_out
ready <<= encrypt_ready
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
sim.step({
self.in_vector: 0x00112233445566778899aabbccddeeff,
aes_key: 0x000102030405060708090a0b0c0d0e0f,
reset: 1
})
true_vals = [
0x00112233445566778899aabbccddeeff,
0x00102030405060708090a0b0c0d0e0f0,
0x89d810e8855ace682d1843d8cb128fe4,
0x4915598f55e5d7a0daca94fa1f0a63f7,
0xfa636a2825b339c940668a3157244d17,
0x247240236966b3fa6ed2753288425b6c,
0xc81677bc9b7ac93b25027992b0261996,
0xc62fe109f75eedc3cc79395d84f9cf5d,
0xd1876c0f79c4300ab45594add66ff41f,
0xfde3bad205e5d0d73547964ef1fe37f1,
0xbd6e7c3df2b5779e0b61216e8b10b689,
0x69c4e0d86a7b0430d8cdb78070b4c55a,
0x69c4e0d86a7b0430d8cdb78070b4c55a,
]
for cycle in range(
1, 13): # Bogus data for while the state machine churns
sim.step({self.in_vector: 0x0, aes_key: 0x1, reset: 0})
circuit_out = sim_trace.trace[self.out_vector][cycle]
sim_trace.render_trace(symbol_len=40)
self.assertEqual(
circuit_out, true_vals[cycle],
"\nAssertion failed on cycle: " + str(cycle) +
" Gotten value: " + hex(circuit_out))
for ready_signal in sim_trace.trace[ready][:11]:
self.assertEquals(ready_signal, 0)
for ready_signal in sim_trace.trace[ready][11:]:
self.assertEquals(ready_signal, 1)
def test_synthesize_unmerged_io_simulates_correctly(self):
pyrtl.synthesize(merge_io_vectors=False)
sim = pyrtl.Simulation()
for (a, b) in [(4, 2), (6, 9), (2, 11), (3, 4)]:
args = {}
for ix in range(4):
args['a[' + str(ix) + ']'] = (a >> ix) & 1
args['b[' + str(ix) + ']'] = (b >> ix) & 1
sim.step(args)
expected = a + b
for ix in range(5):
out = sim.inspect('o[' + str(ix) + ']')
self.assertEqual(out, (expected >> ix) & 1)
def check_rendered_trace(self, expected, **kwargs):
sim = pyrtl.Simulation()
sim.step_multiple({
'a': [1, 4, 9, 11, 12],
'b': [2, 23, 43, 120, 0],
'c': [0, 1, 1, 0, 1]
})
buff = io.StringIO()
sim.tracer.render_trace(file=buff,
render_cls=pyrtl.simulation.AsciiWaveRenderer,
extra_line=False,
**kwargs)
self.assertEqual(buff.getvalue(), expected)
def test_aes_state_machine(self):
# self.longMessage = True
aes_key = pyrtl.Input(bitwidth=128, name='aes_key')
reset = pyrtl.Input(1)
ready = pyrtl.Output(1, name='ready')
decrypt_ready, decrypt_out = self.aes_decrypt.decryption_statem(
self.in_vector, aes_key, reset)
self.out_vector <<= decrypt_out
ready <<= decrypt_ready
sim_trace = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=sim_trace)
sim.step({
self.in_vector: 0x69c4e0d86a7b0430d8cdb78070b4c55a,
aes_key: 0x000102030405060708090a0b0c0d0e0f,
reset: 1
})
true_vals = [
0x69c4e0d86a7b0430d8cdb78070b4c55a,
0x7ad5fda789ef4e272bca100b3d9ff59f,
0x54d990a16ba09ab596bbf40ea111702f,
0x3e1c22c0b6fcbf768da85067f6170495,
0xb458124c68b68a014b99f82e5f15554c,
0xe8dab6901477d4653ff7f5e2e747dd4f,
0x36339d50f9b539269f2c092dc4406d23,
0x2d6d7ef03f33e334093602dd5bfb12c7,
0x3bd92268fc74fb735767cbe0c0590e2d,
0xa7be1a6997ad739bd8c9ca451f618b61,
0x6353e08c0960e104cd70b751bacad0e7,
0x00112233445566778899aabbccddeeff,
0x00112233445566778899aabbccddeeff,
]
for cycle in range(
1, 13): # Bogus data for while the state machine churns
sim.step({self.in_vector: 0x0, aes_key: 0x1, reset: 0})
circuit_out = sim_trace.trace[self.out_vector][cycle]
self.assertEqual(
circuit_out, true_vals[cycle],
"\nAssertion failed on cycle: " + str(cycle) +
" Gotten value: " + hex(circuit_out))
for ready_signal in sim_trace.trace[ready][:11]:
self.assertEquals(ready_signal, 0)
for ready_signal in sim_trace.trace[ready][11:]:
self.assertEquals(ready_signal, 1)
def sim_and_ret_outws(inwires, invals):
""" Simulates the net using inwires and invalues, and returns the output array.
Used for rapid test development.
:param inwires: a list of wires to read in from (`[Input, ...]`)
:param invals: a list of input value lists (`[[int, ...], ...]`)
:return: a list of values from the output wire simulation result
"""
sim_trace = pyrtl.SimulationTrace() # Creating a logger for the simulator
sim = pyrtl.Simulation(tracer=sim_trace) # Creating the simulation
for cycle in range(len(invals[0])):
sim.step({wire.name: val[cycle] for wire, val in zip(inwires, invals)})
return sim_trace.trace # Pulling the value of wires straight from the trace
def test_good_write_to_bundle(self):
x = pyrtl.Input(1, 'x')
def t1():
w = pyrtl.WireVector(8)
with pyrtl.conditional_assignment:
with x:
w |= 0b00101100
with pyrtl.otherwise:
w |= 0b10010011
return w
def t3():
w = pyrtl.WireVector(8)
with pyrtl.conditional_assignment:
with x:
w |= 0b11111111
with pyrtl.otherwise:
w |= 0b00000000
return w
class Array:
# Returning a function which returns a WireVector
thread1 = (8, t1)
# Returning a function with returns a Const with explicit size
thread2 = (8, lambda: pyrtl.Const(0b01100110, 8))
# Returning a WireVector
thread3 = (8, t3())
# Returning a Const without an explicit size
thread4 = (8, pyrtl.Const(0b00000011))
# Returning a literal
thread5 = (8, 0b01000011)
if six.PY3:
w = pyrtl.Bundle(Array, 'w')
sim = pyrtl.Simulation()
sim.step({'x': 1})
assert sim.inspect(w.thread1) == 0b00101100
assert sim.inspect(w.thread2) == 0b01100110
assert sim.inspect(w.thread3) == 0b11111111
assert sim.inspect(w.thread4) == 0b00000011
assert sim.inspect(w.thread5) == 0b01000011
sim.step({'x': 0})
assert sim.inspect(w.thread1) == 0b10010011
assert sim.inspect(w.thread2) == 0b01100110
assert sim.inspect(w.thread3) == 0b00000000
assert sim.inspect(w.thread4) == 0b00000011
assert sim.inspect(w.thread5) == 0b01000011
def test_several_outputs_simulates_correctly(self):
i, j = pyrtl.input_list('i/2 j/2')
o, p, q = pyrtl.output_list('o p q')
o <<= i * j
w = i + 2
p <<= w
q <<= ~w
inputs = [(0, 1), (1, 0), (2, 3), (3, 0), (1, 3)]
trace_pre = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=trace_pre)
for x, y in inputs:
inp_map = {'i': x, 'j': y}
sim.step(inp_map)
pyrtl.direct_connect_outputs()
trace_post = pyrtl.SimulationTrace()
sim = pyrtl.Simulation(tracer=trace_post)
for x, y in inputs:
inp_map = {'i': x, 'j': y}
sim.step(inp_map)
self.assertEqual(trace_pre.trace, trace_post.trace)
