def main():
global max_row, max_col, const_id_count
pytrellis.load_database(database.get_db_root())
args = parser.parse_args()
# Read port pin file
const_id_count = 1 # count ID_NONE
with open(args.constids) as f:
for line in f:
line = line.replace("(", " ")
line = line.replace(")", " ")
line = line.split()
if len(line) == 0:
continue
assert len(line) == 2
assert line[0] == "X"
idx = len(constids) + 1
constids[line[1]] = idx
const_id_count += 1
constids["SLICE"] = constids["TRELLIS_SLICE"]
constids["PIO"] = constids["TRELLIS_IO"]
# print("Initialising chip...")
chip = pytrellis.Chip(dev_names[args.device])
# print("Building routing graph...")
ddrg = pytrellis.make_dedup_chipdb(chip)
max_row = chip.get_max_row()
max_col = chip.get_max_col()
process_timing_data()
process_pio_db(ddrg, args.device)
process_loc_globals(chip)
# print("{} unique location types".format(len(ddrg.locationTypes)))
bba = write_database(args.device, chip, ddrg, "le")
def main():
global max_row, max_col, const_id_count
pytrellis.load_database(database.get_db_root())
args = parser.parse_args()
const_id_count = 1 # count ID_NONE
with open(args.constids) as f:
for line in f:
line = line.replace("(", " ")
line = line.replace(")", " ")
line = line.split()
if len(line) == 0:
continue
assert len(line) == 2
assert line[0] == "X"
idx = len(constids) + 1
constids[line[1]] = idx
const_id_count += 1
constids["SLICE"] = constids["FACADE_SLICE"]
constids["PIO"] = constids["FACADE_IO"]
chip = pytrellis.Chip(dev_names[args.device])
rg = pytrellis.make_optimized_chipdb(chip)
max_row = chip.get_max_row()
max_col = chip.get_max_col()
process_pio_db(rg, args.device)
bba = write_database(args.device, chip, rg, "le")
def main():
global max_row, max_col
pytrellis.load_database(database.get_db_root())
args = parser.parse_args()
# Read port pin file
with open(args.portspins) as f:
for line in f:
line = line.replace("(", " ")
line = line.replace(")", " ")
line = line.split()
if len(line) == 0:
continue
assert len(line) == 2
assert line[0] == "X"
idx = len(portpins) + 1
portpins[line[1]] = idx
# print("Initialising chip...")
chip = pytrellis.Chip(dev_names[args.device])
# print("Building routing graph...")
ddrg = pytrellis.make_dedup_chipdb(chip)
max_row = chip.get_max_row()
max_col = chip.get_max_col()
process_pio_db(ddrg, args.device)
process_loc_globals(chip)
# print("{} unique location types".format(len(ddrg.locationTypes)))
bba = write_database(args.device, chip, ddrg, "le")
def __init__(self, config_data=None):
"""This class handles flashing and evaluating the FPGA bitstream"""
self.chip = pytrellis.Chip(CHIP_NAME)
clean_config_dir()
self.id = get_new_id()
if config_data is not None:
self.load_fpga(config_data)
def main():
pytrellis.load_database("../../../database")
chip = pytrellis.Chip("LCMXO2-1200HC")
tiletypes = set()
for tile in chip.get_all_tiles():
tiletypes.add(tile.info.type)
for tiletype in sorted(tiletypes):
dbfixup.dbfixup("MachXO2", device, tiletype)
def main():
pytrellis.load_database("../../../database")
chip = pytrellis.Chip("LFE5UM5G-45F")
tiletypes = set()
for tile in chip.get_all_tiles():
tiletypes.add(tile.info.type)
for tiletype in sorted(tiletypes):
dbfixup.dbfixup("ECP5", device, tiletype)
def main(argv):
global bitmap, labels
bitmap = dict(dict())
labels = dict(dict())
args = parser.parse_args(argv[1:])
f = args.outfile
print("""<html>
<head><title>{} Bit Data</title>
""".format(args.tile),
file=f)
print("""
<script type="text/javascript">
origClr = {};
origClass = "";
function mov(event) {
if (event.target.className != "unknown") {
origClass = event.target.className;
var elems = document.getElementsByClassName(origClass);
for(var i = 0; i < elems.length; i++) {
if(!(elems[i].id in origClr)) {
origClr[elems[i].id] = elems[i].style.backgroundColor;
}
elems[i].style.backgroundColor = "white";
}
}
}
function mou(event) {
var elems = document.getElementsByClassName(origClass);
for(var i = 0; i < elems.length; i++) {
elems[i].style.backgroundColor = origClr[elems[i].id] || "#ffffff";
}
}
</script>
</head>
<body>
""",
file=f)
print("""<h1>{} Bit Data</h1>
""".format(args.tile), file=f)
pytrellis.load_database(database.get_db_root())
tdb = pytrellis.get_tile_bitdata(
pytrellis.TileLocator(args.family, args.device, args.tile))
ch = pytrellis.Chip(args.device)
ti = ch.get_tiles_by_type(args.tile)[0].info
find_bits(tdb)
bit_grid_html(ti, f)
muxes_html(tdb, f)
setwords_html(tdb, f)
setenums_html(tdb, f)
fixed_conns_html(tdb, f)
print("""</body></html>""", file=f)
def main():
pytrellis.load_database(database.get_db_root())
chip = pytrellis.Chip("LFE5U-45F")
rt = Autorouter(chip)
config = {_.info.name: pytrellis.TileConfig() for _ in chip.get_all_tiles()}
rt.bind_net_to_port("x", "R15C10_Q0")
rt.route_net_to_wire("x", "R15C50_A0", config)
for tile, tcfg in sorted(config.items()):
cfgtext = tcfg.to_string()
if len(cfgtext.strip()) > 0:
print(".tile {}".format(tile))
print(cfgtext)
def get_device_tiles(family, devices):
all_tiles = set()
fd_tiles = {}
for dev, devdata in sorted(devices.items()):
if devdata["fuzz"]:
fd_tiles[family, dev] = []
c = pytrellis.Chip(dev)
for tile in c.get_all_tiles():
tt = tile.info.type
if tt not in all_tiles:
all_tiles.add(tt)
fd_tiles[family, dev].append(tt)
return fd_tiles
def __init__(self, family):
self.chip = pytrellis.Chip("LFE5U-45F")
self.bias = self.chip.info.col_bias
self.router = route.Autorouter(self.chip)
self.config = {_.info.name: pytrellis.TileConfig() for _ in self.chip.get_all_tiles()}
# TODO: load skeleton config
self.bels = dict()
self.bel_to_cell = {}
self.bels_by_type = {}
self.auto_netid = 0
self.auto_cellid = 0
self.init_bels()
def main():
pytrellis.load_database(database.get_db_root())
c = pytrellis.Chip("LFE5U-45F")
chip_size = (c.get_max_row(), c.get_max_col())
# Get fan-in to a net
# Returns (source, configurable, loc)
def get_fanin(net):
drivers = []
npos = tiles.pos_from_name(net)
for tile in c.get_all_tiles():
tinf = tile.info
tname = tinf.name
pos = tiles.pos_from_name(tname)
if abs(pos[0] - npos[0]) >= 10 or abs(pos[1] - npos[1]) >= 10:
continue
if net.startswith("G_"):
tnet = net
else:
tnet = nets.normalise_name(chip_size, tname, net)
tdb = pytrellis.get_tile_bitdata(
pytrellis.TileLocator(c.info.family, c.info.name, tinf.type))
try:
mux = tdb.get_mux_data_for_sink(tnet)
for src in mux.get_sources():
drivers.append(
(nets.canonicalise_name(chip_size, tname,
src), True, tname))
except IndexError:
pass
for fc in tdb.get_fixed_conns():
if fc.sink == tnet:
drivers.append(
(nets.canonicalise_name(chip_size, tname,
fc.source), False, tname))
return drivers
# Get fan-out of a net
# Returns (dest, configurable, loc)
def get_fanout(net):
drivers = []
npos = tiles.pos_from_name(net)
for tile in c.get_all_tiles():
tinf = tile.info
tname = tinf.name
pos = tiles.pos_from_name(tname)
if abs(pos[0] - npos[0]) >= 12 or abs(pos[1] - npos[1]) >= 12:
continue
if net.startswith("G_"):
tnet = net
else:
tnet = nets.normalise_name(chip_size, tname, net)
tdb = pytrellis.get_tile_bitdata(
pytrellis.TileLocator(c.info.family, c.info.name, tinf.type))
for sink in tdb.get_sinks():
mux = tdb.get_mux_data_for_sink(sink)
if tnet in mux.arcs:
drivers.append(
(nets.canonicalise_name(chip_size, tname,
sink), True, tname))
for fc in tdb.get_fixed_conns():
if fc.source == tnet:
drivers.append(
(nets.canonicalise_name(chip_size, tname,
fc.sink), False, tname))
return drivers
# Get all nets at a location
net_tile_cache = {}
non_tile_re = re.compile(r"^([NS]\d+)?([EW]\d+)?[GLR]?_.*")
def get_nets_at(loc):
if loc in net_tile_cache:
return net_tile_cache[loc]
row, col = loc
nets = set()
for tile in c.get_tiles_by_position(row, col):
tinf = tile.info
tdb = pytrellis.get_tile_bitdata(
pytrellis.TileLocator(c.info.family, c.info.name, tinf.type))
for sink in tdb.get_sinks():
if not non_tile_re.match(sink):
nets.add(sink)
mux = tdb.get_mux_data_for_sink(sink)
for src in mux.get_sources():
if not non_tile_re.match(src):
nets.add(src)
for fc in tdb.get_fixed_conns():
if not non_tile_re.match(fc.sink):
nets.add(fc.sink)
if not non_tile_re.match(fc.source):
nets.add(fc.source)
nets = list(sorted((["R{}C{}_{}".format(row, col, _) for _ in nets])))
net_tile_cache[loc] = nets
return nets
tile_net_re = re.compile(r"^R\d+C\d+_.*")
def completer(str, idx):
if not tile_net_re.match(str):
return None
loc = tiles.pos_from_name(str)
nets = get_nets_at(loc)
for n in nets:
if n.startswith(str):
if idx > 0:
idx -= 1
else:
return n
return None
readline.parse_and_bind("tab: complete")
readline.set_completer(completer)
hist_buf = []
while True:
net = input("> ")
if net.strip() == "":
continue
if net == "quit":
return
if net.isdigit():
idx = int(net)
if idx >= len(hist_buf):
print("Invalid index into last result")
continue
else:
net = hist_buf[idx]
if not tile_net_re.match(net):
print("Bad netname, expected RyCx_...")
continue
hist_buf = []
fi = get_fanin(net)
for drv in fi:
finet, conf, tile = drv
if finet is None: continue
arrow = "<--" if conf else "<=="
print("[{:3d}] {} {} {:25s} [in {}]".format(
len(hist_buf), net, arrow, finet, tile))
hist_buf.append(finet)
print()
fo = get_fanout(net)
for src in fo:
fonet, conf, tile = src
if fonet is None: continue
arrow = "-->" if conf else "==>"
print("[{:3d}] {} {} {:25s} [in {}]".format(
len(hist_buf), net, arrow, fonet, tile))
hist_buf.append(fonet)
#!/usr/bin/env python3
import pytrellis
pytrellis.load_database("./testdata")
c = pytrellis.Chip("testdev")
assert c.get_max_row() == 0
assert c.get_max_col() == 0
bits = {
(0, 0),
(0, 3),
(1, 0),
(1, 2),
(2, 0),
(5, 3)
}
for b in bits:
c.cram.set_bit(10 + b[0], 15 + b[1], 1)
tcram = c.tiles["TEST_R0C0:TESTTILE"].cram
assert tcram.frames() == 20
assert tcram.bits() == 10
tl = pytrellis.TileLocator("test", "testdev", "TESTTILE")
tiledb = pytrellis.get_tile_bitdata(tl)
cfg = tiledb.tile_cram_to_config(tcram)
assert len(cfg.carcs) == 1
assert cfg.carcs[0].source == "H2" and cfg.carcs[0].sink == "A0"
assert len(cfg.cwords) == 1
def main(args):
global max_row, max_col
pytrellis.load_database(database.get_db_root())
chip = pytrellis.Chip(args.device)
max_row = chip.get_max_row()
max_col = chip.get_max_col()
if chip.info.family == "MachXO2":
# I/O Grouping is present in MachXO2 pinouts but not ECP5.
pkg_index_start = 8
else:
pkg_index_start = 7
metadata = dict()
package_data = dict()
package_indicies = None
found_header = False
with args.infile as csvf:
for line in csvf:
trline = line.strip()
splitline = trline.split(",")
if len(splitline) < (pkg_index_start + 1):
continue
if len(splitline[0].strip()) == 0:
continue
if splitline[0] == "PAD":
# is header
found_header = True
package_indicies = splitline[pkg_index_start:]
for pkg in package_indicies:
package_data[pkg] = {}
elif found_header:
if splitline[1][0] != "P" or splitline[1].startswith(
"PROGRAM"):
continue
bel = get_bel(splitline[1])
bank = int(splitline[2])
function = splitline[3]
dqs = splitline[6]
if chip.info.family == "MachXO2":
io_grouping = splitline[7]
metadata[bel] = bank, function, dqs, io_grouping
else:
metadata[bel] = bank, function, dqs
for i in range(len(package_indicies)):
if splitline[pkg_index_start + i] == "-":
continue
package_data[package_indicies[i]][splitline[pkg_index_start
+ i]] = bel
json_data = {"packages": {}, "pio_metadata": []}
for pkg, pins in package_data.items():
json_data["packages"][pkg] = {}
for pin, bel in pins.items():
json_data["packages"][pkg][pin] = {
"col": bel[0],
"row": bel[1],
"pio": bel[2]
}
for bel, data in sorted(metadata.items()):
if chip.info.family == "MachXO2":
bank, function, dqs, io_grouping = data
else:
bank, function, dqs = data
meta = {"col": bel[0], "row": bel[1], "pio": bel[2], "bank": bank}
if function != "-":
meta["function"] = function
if dqs != "-":
meta["dqs"] = dqs
if chip.info.family == "MachXO2":
# Since "+" is used, "-" means "minus" presumably, as opposed to
# "not applicable".
meta["io_grouping"] = io_grouping
json_data["pio_metadata"].append(meta)
with args.outfile as jsonf:
jsonf.write(
json.dumps(json_data,
sort_keys=True,
indent=4,
separators=(',', ': ')))
import pytrellis
import database
pytrellis.load_database(database.get_db_root())
chip = pytrellis.Chip("LFE5U-12F")
graph = chip.get_routing_graph()
tile = graph.tiles[pytrellis.Location(12, 6)]
def rid_to_arc(routingId):
return graph.tiles[routingId.loc].arcs[routingId.id]
def rid_to_wire(routingId):
return graph.tiles[routingId.loc].wires[routingId.id]
def rid_to_bel(bel):
return graph.tiles[bel.loc].bels[bel.id]
routingBelIds = dict()
routingPortIds = dict()
routingArcIds = dict()
routingWiresIds = dict()
foreignRoutingWiresIds = dict()
counter = 0
toBeMatched = set()
for arc in [
x.data() for x in tile.arcs if x.data().source.loc == tile.loc and (
#!/usr/bin/env python3
"""
Testing the routing graph generator
"""
import pytrellis
import sys
pytrellis.load_database("../../database")
chip = pytrellis.Chip("LFE5U-45F")
rg = chip.get_routing_graph()
tile = rg.tiles[pytrellis.Location(9, 71)]
for wire in tile.wires:
print("Wire {}:".format(rg.to_str(wire.key())))
for dh in wire.data().downhill:
arc = rg.tiles[dh.loc].arcs[dh.id]
print(" --> R{}C{}_{}".format(arc.sink.loc.y, arc.sink.loc.x,
rg.to_str(arc.sink.id)))
for bdh in wire.data().belsDownhill:
print(" ->| R{}C{}_{}.{}".format(bdh.bel.loc.y, bdh.bel.loc.x,
rg.to_str(bdh.bel.id),
rg.to_str(bdh.pin)))
print()
for uh in wire.data().uphill:
arc = rg.tiles[uh.loc].arcs[uh.id]
print(" <-- R{}C{}_{}".format(arc.source.loc.y, arc.source.loc.x,
rg.to_str(arc.source.id)))
for buh in wire.data().belsUphill:
print(" <-| R{}C{}_{}.{}".format(buh.bel.loc.y, buh.bel.loc.x,
rg.to_str(buh.bel.id),
rg.to_str(buh.pin)))
print()
