def test_get_layered_instructions_left_justification_simple(self):
"""Test _get_layered_instructions left justification simple since #2802
q_0: |0>───────■──
┌───┐ │
q_1: |0>┤ H ├──┼──
├───┤ │
q_2: |0>┤ H ├──┼──
└───┘┌─┴─┐
q_3: |0>─────┤ X ├
└───┘
"""
qc = QuantumCircuit(4)
qc.h(1)
qc.h(2)
qc.cx(0, 3)
(_, _, layered_ops) = utils._get_layered_instructions(qc,
justify="left")
l_exp = [
[
("h", [Qubit(QuantumRegister(4, "q"), 1)], []),
("h", [Qubit(QuantumRegister(4, "q"), 2)], []),
],
[("cx", [
Qubit(QuantumRegister(4, "q"), 0),
Qubit(QuantumRegister(4, "q"), 3)
], [])],
]
self.assertEqual(l_exp, [[(op.name, op.qargs, op.cargs) for op in ops]
for ops in layered_ops])
def test_nested_loop(self):
"""Test a simple if-else with parameters."""
qubits = [Qubit(), Qubit()]
clbits = [Clbit(), Clbit()]
cr = ClassicalRegister(bits=clbits)
index1 = Parameter("index1")
alpha = Parameter("alpha")
gate = OneQubitOneParamGate(alpha)
equiv = QuantumCircuit([qubits[0]])
equiv.append(OneQubitZeroParamGate(name="1q0p_2"), [qubits[0]])
equiv.append(OneQubitOneParamGate(alpha, name="1q1p_2"), [qubits[0]])
eq_lib = EquivalenceLibrary()
eq_lib.add_equivalence(gate, equiv)
circ = QuantumCircuit(qubits, cr)
with circ.for_loop(range(3), loop_parameter=index1) as ind:
with circ.while_loop((cr, 0)):
circ.append(OneQubitOneParamGate(alpha * ind), [qubits[0]])
dag = circuit_to_dag(circ)
dag_translated = BasisTranslator(
eq_lib,
["if_else", "for_loop", "while_loop", "1q0p_2", "1q1p_2"]).run(dag)
expected = QuantumCircuit(qubits, cr)
with expected.for_loop(range(3), loop_parameter=index1) as ind:
with expected.while_loop((cr, 0)):
expected.append(OneQubitZeroParamGate(name="1q0p_2"),
[qubits[0]])
expected.append(
OneQubitOneParamGate(alpha * ind, name="1q1p_2"),
[qubits[0]])
dag_expected = circuit_to_dag(expected)
self.assertEqual(dag_translated, dag_expected)
def test_instructionset_c_if_with_no_requester(self):
"""Test that using a raw :obj:`.InstructionSet` with no classical-resource resoluer accepts
arbitrary :obj:`.Clbit` and `:obj:`.ClassicalRegister` instances, but rejects integers."""
with self.subTest("accepts arbitrary register"):
instruction = HGate()
instructions = InstructionSet()
instructions.add(instruction, [Qubit()], [])
register = ClassicalRegister(2)
instructions.c_if(register, 0)
self.assertIs(instruction.condition[0], register)
with self.subTest("accepts arbitrary bit"):
instruction = HGate()
instructions = InstructionSet()
instructions.add(instruction, [Qubit()], [])
bit = Clbit()
instructions.c_if(bit, 0)
self.assertIs(instruction.condition[0], bit)
with self.subTest("rejects index"):
instruction = HGate()
instructions = InstructionSet()
instructions.add(instruction, [Qubit()], [])
with self.assertRaisesRegex(
CircuitError, r"Cannot pass an index as a condition .*"):
instructions.c_if(0, 0)
def depGraphToDag(self, dep_graph, registers_in_order):
# first add the registers in the proper order
dag = DAGCircuit()
already_added = {
} # registers may yield mutliple wires, we don't want to add them multiple times
for qubit in registers_in_order:
if already_added.get(qubit.register) is None:
already_added[qubit.register] = True
dag.add_qreg(qubit.register)
for dep_node in dep_graph.nodesInTopologicalOrder():
if dep_node.gate.name == 'init':
if already_added.get(dep_node.register) is None:
already_added[dep_node.register] = True
dag.add_qreg(dep_node.register)
else:
#get the arguments of the gate: again assuming ctrls first, target last
ctrl_reg = [
Qubit(ctrl_edge.node_from.register,
ctrl_edge.node_from.index)
for ctrl_edge in dep_node.ctrl_edges_in
]
target_reg = Qubit(dep_node.consume_edge_in.node_from.register,
dep_node.consume_edge_in.node_from.index)
ctrl_reg.append(target_reg)
dag.apply_operation_back(dep_node.gate, ctrl_reg)
return dag
def test_registerless_one_bit(self):
"""Test circuit with one-bit registers and registerless bits."""
qrx = QuantumRegister(2, "qrx")
qry = QuantumRegister(1, "qry")
crx = ClassicalRegister(2, "crx")
circuit = QuantumCircuit(qrx, [Qubit(), Qubit()], qry, [Clbit(), Clbit()], crx)
self.circuit_drawer(circuit, filename="registerless_one_bit.png")
def test_get_layered_instructions_right_justification_simple(self):
""" Test _get_layered_instructions right justification simple since #2802
q_0: |0>──■───────
│ ┌───┐
q_1: |0>──┼──┤ H ├
│ ├───┤
q_2: |0>──┼──┤ H ├
┌─┴─┐└───┘
q_3: |0>┤ X ├─────
└───┘
"""
qc = QuantumCircuit(4)
qc.h(1)
qc.h(2)
qc.cx(0, 3)
(_, _, layered_ops) = utils._get_layered_instructions(qc, justify='right')
r_exp = [[('cx', [Qubit(QuantumRegister(4, 'q'), 0),
Qubit(QuantumRegister(4, 'q'), 3)], [])],
[('h', [Qubit(QuantumRegister(4, 'q'), 1)], []),
('h', [Qubit(QuantumRegister(4, 'q'), 2)], [])
]
]
self.assertEqual(r_exp,
[[(op.name, op.qargs, op.cargs) for op in ops] for ops in layered_ops])
def test_get_layered_instructions_op_with_cargs(self):
""" Test _get_layered_instructions op with cargs right of measure
┌───┐┌─┐
q_0: |0>┤ H ├┤M├─────────────
└───┘└╥┘┌───────────┐
q_1: |0>──────╫─┤0 ├
║ │ add_circ │
c_0: 0 ══════╩═╡0 ╞
└───────────┘
c_1: 0 ═════════════════════
"""
qc = QuantumCircuit(2, 2)
qc.h(0)
qc.measure(0, 0)
qc_2 = QuantumCircuit(1, 1, name='add_circ')
qc_2.h(0).c_if(qc_2.cregs[0], 1)
qc_2.measure(0, 0)
qc.append(qc_2, [1], [0])
(_, _, layered_ops) = utils._get_layered_instructions(qc)
expected = [[('h', [Qubit(QuantumRegister(2, 'q'), 0)], [])],
[('measure', [Qubit(QuantumRegister(2, 'q'), 0)],
[Clbit(ClassicalRegister(2, 'c'), 0)])],
[('add_circ', [Qubit(QuantumRegister(2, 'q'), 1)],
[Clbit(ClassicalRegister(2, 'c'), 0)])]]
self.assertEqual(expected, [[(op.name, op.qargs, op.cargs)
for op in ops] for ops in layered_ops])
def test_if_simple(self):
"""Test a simple if statement unrolls correctly."""
qubits = [Qubit(), Qubit()]
clbits = [Clbit(), Clbit()]
qc = QuantumCircuit(qubits, clbits)
qc.h(0)
qc.measure(0, 0)
with qc.if_test((clbits[0], 0)):
qc.x(0)
qc.h(0)
qc.measure(0, 1)
with qc.if_test((clbits[1], 0)):
qc.h(1)
qc.cx(1, 0)
dag = circuit_to_dag(qc)
unrolled_dag = Unroller(["u", "cx"]).run(dag)
expected = QuantumCircuit(qubits, clbits)
expected.u(pi / 2, 0, pi, 0)
expected.measure(0, 0)
with expected.if_test((clbits[0], 0)):
expected.u(pi, 0, pi, 0)
expected.u(pi / 2, 0, pi, 0)
expected.measure(0, 1)
with expected.if_test((clbits[1], 0)):
expected.u(pi / 2, 0, pi, 1)
expected.cx(1, 0)
expected_dag = circuit_to_dag(expected)
self.assertEqual(unrolled_dag, expected_dag)
def test_compose_noclbits_registerless(self):
"""Combining a circuit with cregs to one without, registerless case"""
inner = QuantumCircuit([Qubit(), Qubit()], [Clbit(), Clbit()])
inner.measure([0, 1], [0, 1])
outer = QuantumCircuit(2)
outer.compose(inner, inplace=True)
self.assertEqual(outer.clbits, inner.clbits)
self.assertEqual(outer.cregs, [])
def remove_qubits(qc):
register_list = qc.qregs
# list of used qubits
used_qubit_list = {}
for gate in qc:
for qubit in gate[1]:
used_qubit_list.setdefault(qubit, 1)
while len(used_qubit_list) != len(qc.qubits):
# These 4 lines were added after experiments except
used_qubit_list = {}
for gate in qc:
for qubit in gate[1]:
used_qubit_list.setdefault(qubit, 1)
for qubit in qc.qubits:
if (qubit in used_qubit_list) == False:
del_index = qubit._index
del_register = qubit._register
register_list.remove(del_register)
if qubit._register.size > 1:
new_register = QuantumRegister(
qubit._register.size - 1, qubit._register.name)
register_list.append(new_register)
gate_list = []
for gate in qc:
qubit_list = gate[1]
for x in range(len(qubit_list)):
if qubit_list[x]._register == del_register:
if qubit_list[x]._index < del_index:
qubit_list[x] = Qubit(
new_register, qubit_list[x]._index)
else:
qubit_list[x] = Qubit(
new_register,
qubit_list[x]._index - 1)
gate_list.append(gate)
else:
gate_list = []
for gate in qc:
gate_list.append(gate)
qc = QuantumCircuit(*register_list, *qc.cregs)
for gate in gate_list:
qc.append(gate[0], gate[1], gate[2])
break
return qc
def test_instructionset_c_if_calls_custom_requester(self):
"""Test that :meth:`.InstructionSet.c_if` calls a custom requester, and uses its output."""
# This isn't expected to be useful to end users, it's more about the principle that you can
# control the resolution paths, so future blocking constructs can forbid the method from
# accessing certain resources.
sentinel_bit = Clbit()
sentinel_register = ClassicalRegister(2)
def dummy_requester(specifier):
"""A dummy requester that returns sentinel values."""
if not isinstance(specifier, (int, Clbit, ClassicalRegister)):
raise CircuitError
return sentinel_bit if isinstance(specifier,
(int,
Clbit)) else sentinel_register
dummy_requester = unittest.mock.MagicMock(wraps=dummy_requester)
with self.subTest("calls requester with bit"):
dummy_requester.reset_mock()
instruction = HGate()
instructions = InstructionSet(resource_requester=dummy_requester)
instructions.add(instruction, [Qubit()], [])
bit = Clbit()
instructions.c_if(bit, 0)
dummy_requester.assert_called_once_with(bit)
self.assertIs(instruction.condition[0], sentinel_bit)
with self.subTest("calls requester with index"):
dummy_requester.reset_mock()
instruction = HGate()
instructions = InstructionSet(resource_requester=dummy_requester)
instructions.add(instruction, [Qubit()], [])
index = 0
instructions.c_if(index, 0)
dummy_requester.assert_called_once_with(index)
self.assertIs(instruction.condition[0], sentinel_bit)
with self.subTest("calls requester with register"):
dummy_requester.reset_mock()
instruction = HGate()
instructions = InstructionSet(resource_requester=dummy_requester)
instructions.add(instruction, [Qubit()], [])
register = ClassicalRegister(2)
instructions.c_if(register, 0)
dummy_requester.assert_called_once_with(register)
self.assertIs(instruction.condition[0], sentinel_register)
with self.subTest("calls requester only once when broadcast"):
dummy_requester.reset_mock()
instruction_list = [HGate(), HGate(), HGate()]
instructions = InstructionSet(resource_requester=dummy_requester)
for instruction in instruction_list:
instructions.add(instruction, [Qubit()], [])
register = ClassicalRegister(2)
instructions.c_if(register, 0)
dummy_requester.assert_called_once_with(register)
for instruction in instruction_list:
self.assertIs(instruction.condition[0], sentinel_register)
def test_registerless_one_bit(self):
"""Text circuit with one-bit registers and registerless bits."""
filename = self._get_resource_path("test_latex_registerless_one_bit.tex")
qrx = QuantumRegister(2, "qrx")
qry = QuantumRegister(1, "qry")
crx = ClassicalRegister(2, "crx")
circuit = QuantumCircuit(qrx, [Qubit(), Qubit()], qry, [Clbit(), Clbit()], crx)
circuit_drawer(circuit, filename=filename, output="latex_source")
self.assertEqualToReference(filename)
def test_conditions_measures_with_bits(self):
"""Test that gates with conditions and measures work with bits"""
bits = [Qubit(), Qubit(), Clbit(), Clbit()]
cr = ClassicalRegister(2, "cr")
crx = ClassicalRegister(3, "cs")
circuit = QuantumCircuit(bits, cr, [Clbit()], crx)
circuit.x(0).c_if(crx[1], 0)
circuit.measure(0, bits[3])
self.circuit_drawer(circuit, cregbundle=False, filename="measure_cond_bits_false.png")
self.circuit_drawer(circuit, cregbundle=True, filename="measure_cond_bits_true.png")
def test_conditions_with_bits_reverse(self):
"""Test that gates with conditions work with bits reversed"""
bits = [Qubit(), Qubit(), Clbit(), Clbit()]
cr = ClassicalRegister(2, "cr")
crx = ClassicalRegister(2, "cs")
circuit = QuantumCircuit(bits, cr, [Clbit()], crx)
circuit.x(0).c_if(bits[3], 0)
self.circuit_drawer(
circuit, cregbundle=False, reverse_bits=True, filename="cond_bits_reverse.png"
)
def test_apply_operation_back_conditional_measure(self):
"""Test consistency of apply_operation_back for conditional measure."""
# Measure targeting a clbit which is not a member of the conditional
# register. qc.measure(qr[0], cr[0]).c_if(cr2, 0)
new_creg = ClassicalRegister(1, 'cr2')
self.dag.add_creg(new_creg)
meas_gate = Measure()
meas_gate.control = (new_creg, 0)
meas_node = self.dag.apply_operation_back(meas_gate, [self.qubit0],
[self.clbit0],
meas_gate.control)
self.assertEqual(meas_node.qargs, [self.qubit0])
self.assertEqual(meas_node.cargs, [self.clbit0])
self.assertEqual(meas_node.condition, meas_gate.control)
self.assertEqual(
sorted(self.dag._multi_graph.in_edges(meas_node, data=True)),
sorted([
(self.dag.input_map[self.qubit0], meas_node, {
'wire': Qubit(*self.qubit0),
'name': 'qr[0]'
}),
(self.dag.input_map[self.clbit0], meas_node, {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(self.dag.input_map[new_creg[0]], meas_node, {
'wire': Clbit(new_creg, 0),
'name': 'cr2[0]'
}),
]))
self.assertEqual(
sorted(self.dag._multi_graph.out_edges(meas_node, data=True)),
sorted([
(meas_node, self.dag.output_map[self.qubit0], {
'wire': Qubit(*self.qubit0),
'name': 'qr[0]'
}),
(meas_node, self.dag.output_map[self.clbit0], {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(meas_node, self.dag.output_map[new_creg[0]], {
'wire': Clbit(new_creg, 0),
'name': 'cr2[0]'
}),
]))
self.assertTrue(nx.is_directed_acyclic_graph(self.dag._multi_graph))
def test_conditions_with_bits_reverse(self):
"""Test that gates with conditions and measures work with bits reversed"""
filename = self._get_resource_path("test_latex_cond_reverse.tex")
bits = [Qubit(), Qubit(), Clbit(), Clbit()]
cr = ClassicalRegister(2, "cr")
crx = ClassicalRegister(3, "cs")
circuit = QuantumCircuit(bits, cr, [Clbit()], crx)
circuit.x(0).c_if(bits[3], 0)
circuit_drawer(
circuit, cregbundle=False, reverse_bits=True, filename=filename, output="latex_source"
)
self.assertEqualToReference(filename)
def test_all_1q_score(self):
"""Test error rate for all 1q input."""
bit_map = {Qubit(): 0, Qubit(): 1}
reverse_bit_map = {v: k for k, v in bit_map.items()}
im_graph = retworkx.PyDiGraph()
im_graph.add_node({"sx": 1})
im_graph.add_node({"sx": 1})
backend = FakeYorktownV2()
vf2_pass = VF2PostLayout(target=backend.target)
layout = Layout(bit_map)
score = vf2_pass._score_layout(layout, bit_map, reverse_bit_map,
im_graph)
self.assertAlmostEqual(0.002925, score, places=5)
def test_apply_operation_back_conditional_measure_to_self(self):
"""Test consistency of apply_operation_back for measure onto conditioning bit."""
# Measure targeting a clbit which _is_ a member of the conditional
# register. qc.measure(qr[0], cr[0]).c_if(cr, 3)
meas_gate = Measure()
meas_gate.control = self.condition
meas_node = self.dag.apply_operation_back(meas_gate, [self.qubit1],
[self.clbit1],
self.condition)
self.assertEqual(meas_node.qargs, [self.qubit1])
self.assertEqual(meas_node.cargs, [self.clbit1])
self.assertEqual(meas_node.condition, meas_gate.control)
self.assertEqual(
sorted(self.dag._multi_graph.in_edges(meas_node, data=True)),
sorted([
(self.dag.input_map[self.qubit1], meas_node, {
'wire': Qubit(*self.qubit1),
'name': 'qr[1]'
}),
(self.dag.input_map[self.clbit0], meas_node, {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(self.dag.input_map[self.clbit1], meas_node, {
'wire': Clbit(*self.clbit1),
'name': 'cr[1]'
}),
]))
self.assertEqual(
sorted(self.dag._multi_graph.out_edges(meas_node, data=True)),
sorted([
(meas_node, self.dag.output_map[self.qubit1], {
'wire': Qubit(*self.qubit1),
'name': 'qr[1]'
}),
(meas_node, self.dag.output_map[self.clbit0], {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(meas_node, self.dag.output_map[self.clbit1], {
'wire': Clbit(*self.clbit1),
'name': 'cr[1]'
}),
]))
self.assertTrue(nx.is_directed_acyclic_graph(self.dag._multi_graph))
def test_measures_with_conditions_with_bits(self):
"""Condition and measure on single bits cregbundle true"""
filename1 = self._get_resource_path("test_latex_meas_cond_bits_false.tex")
filename2 = self._get_resource_path("test_latex_meas_cond_bits_true.tex")
bits = [Qubit(), Qubit(), Clbit(), Clbit()]
cr = ClassicalRegister(2, "cr")
crx = ClassicalRegister(3, "cs")
circuit = QuantumCircuit(bits, cr, [Clbit()], crx)
circuit.x(0).c_if(crx[1], 0)
circuit.measure(0, bits[3])
circuit_drawer(circuit, cregbundle=False, filename=filename1, output="latex_source")
circuit_drawer(circuit, cregbundle=True, filename=filename2, output="latex_source")
self.assertEqualToReference(filename1)
self.assertEqualToReference(filename2)
def test_circuit_constructor_on_bits(self):
"""Verify we can add bits directly to a circuit."""
qubits = [Qubit(), Qubit()]
clbits = [Clbit()]
ancillas = [AncillaQubit(), AncillaQubit()]
qc = QuantumCircuit(qubits, clbits, ancillas)
self.assertEqual(qc.qubits, qubits + ancillas)
self.assertEqual(qc.clbits, clbits)
self.assertEqual(qc.ancillas, ancillas)
self.assertEqual(qc.qregs, [])
self.assertEqual(qc.cregs, [])
def test_apply_operation_back_conditional(self):
"""Test consistency of apply_operation_back with condition set."""
# Single qubit gate conditional: qc.h(qr[2]).c_if(cr, 3)
h_gate = HGate()
h_gate.control = self.condition
h_node = self.dag.apply_operation_back(h_gate, [self.qubit2], [],
h_gate.control)
self.assertEqual(h_node.qargs, [self.qubit2])
self.assertEqual(h_node.cargs, [])
self.assertEqual(h_node.condition, h_gate.control)
self.assertEqual(
sorted(self.dag._multi_graph.in_edges(h_node, data=True)),
sorted([
(self.dag.input_map[self.qubit2], h_node, {
'wire': Qubit(*self.qubit2),
'name': 'qr[2]'
}),
(self.dag.input_map[self.clbit0], h_node, {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(self.dag.input_map[self.clbit1], h_node, {
'wire': Clbit(*self.clbit1),
'name': 'cr[1]'
}),
]))
self.assertEqual(
sorted(self.dag._multi_graph.out_edges(h_node, data=True)),
sorted([
(h_node, self.dag.output_map[self.qubit2], {
'wire': Qubit(*self.qubit2),
'name': 'qr[2]'
}),
(h_node, self.dag.output_map[self.clbit0], {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(h_node, self.dag.output_map[self.clbit1], {
'wire': Clbit(*self.clbit1),
'name': 'cr[1]'
}),
]))
self.assertTrue(nx.is_directed_acyclic_graph(self.dag._multi_graph))
def test_all_1q_avg_score(self):
"""Test average scoring for all 1q input."""
bit_map = {Qubit(): 0, Qubit(): 1}
reverse_bit_map = {v: k for k, v in bit_map.items()}
im_graph = retworkx.PyDiGraph()
im_graph.add_node({"sx": 1})
im_graph.add_node({"sx": 1})
backend = FakeYorktownV2()
vf2_pass = VF2PostLayout(target=backend.target)
vf2_pass.avg_error_map = vf2_utils.build_average_error_map(
vf2_pass.target, vf2_pass.properties, vf2_pass.coupling_map)
layout = Layout(bit_map)
score = vf2_utils.score_layout(vf2_pass.avg_error_map, layout, bit_map,
reverse_bit_map, im_graph)
self.assertAlmostEqual(0.02054, score, places=5)
def test_mixed_register_and_registerless_indexing(self):
"""Test indexing if circuit contains bits in and out of registers."""
bits = [Qubit(), Qubit()]
qreg = QuantumRegister(3, "q")
circuit = QuantumCircuit(bits, qreg)
for i in range(len(circuit.qubits)):
circuit.rz(i, i)
expected_qubit_order = bits + qreg[:]
expected_circuit = QuantumCircuit(bits, qreg)
for i in range(len(expected_circuit.qubits)):
expected_circuit.rz(i, expected_qubit_order[i])
self.assertEqual(circuit.data, expected_circuit.data)
def test_circuit_qasm_with_registerless_bits(self):
"""Test that registerless bits do not have naming collisions in their registers."""
initial_registers = [QuantumRegister(2), ClassicalRegister(2)]
qc = QuantumCircuit(*initial_registers, [Qubit(), Clbit()])
# Match a 'qreg identifier[3];'-like QASM register declaration.
register_regex = re.compile(r"\s*[cq]reg\s+(\w+)\s*\[\d+\]\s*", re.M)
qasm_register_names = set()
for statement in qc.qasm().split(";"):
match = register_regex.match(statement)
if match:
qasm_register_names.add(match.group(1))
self.assertEqual(len(qasm_register_names), 4)
# Check that no additional registers were added to the circuit.
self.assertEqual(len(qc.qregs), 1)
self.assertEqual(len(qc.cregs), 1)
# Check that the registerless-register names are recalculated after adding more registers,
# to avoid naming clashes in this case.
generated_names = qasm_register_names - {
register.name
for register in initial_registers
}
for generated_name in generated_names:
qc.add_register(QuantumRegister(1, name=generated_name))
qasm_register_names = set()
for statement in qc.qasm().split(";"):
match = register_regex.match(statement)
if match:
qasm_register_names.add(match.group(1))
self.assertEqual(len(qasm_register_names), 6)
def test_circuit_with_registerless_bits(self):
"""Test a circuit with registerless bits can be converted to a gate."""
qr1 = QuantumRegister(2)
qubits = [Qubit(), Qubit(), Qubit()]
qr2 = QuantumRegister(3)
circ = QuantumCircuit(qr1, qubits, qr2)
circ.cx(3, 5)
gate = circ.to_gate()
self.assertIsInstance(gate, Gate)
self.assertEqual(gate.num_qubits, len(qr1) + len(qubits) + len(qr2))
gate_definition = gate.definition
cx = gate_definition.data[0]
self.assertEqual(
cx.qubits, (gate_definition.qubits[3], gate_definition.qubits[5]))
self.assertEqual(cx.clbits, ())
def test_instructionset_c_if_direct_resource(self):
"""Test that using :meth:`.InstructionSet.c_if` with an exact classical resource always
works, and produces the expected condition."""
cr1 = ClassicalRegister(3)
qubits = [Qubit()]
loose_clbits = [Clbit(), Clbit(), Clbit()]
# These bits are going into registers which overlap.
register_clbits = [Clbit(), Clbit(), Clbit()]
cr2 = ClassicalRegister(bits=register_clbits[:2])
cr3 = ClassicalRegister(bits=register_clbits[1:])
def case(resource):
qc = QuantumCircuit(cr1, qubits, loose_clbits, cr2, cr3)
qc.x(0).c_if(resource, 0)
c_if_resource = qc.data[0].operation.condition[0]
self.assertIs(c_if_resource, resource)
with self.subTest("classical register"):
case(cr1)
with self.subTest("bit from classical register"):
case(cr1[0])
with self.subTest("loose bit"):
case(loose_clbits[0])
with self.subTest("overlapping register left"):
case(cr2)
with self.subTest("overlapping register right"):
case(cr3)
with self.subTest("bit in two different registers"):
case(register_clbits[1])
def test_inserted_ancilla_bits_are_added_to_qubits(self):
"""Verify AncillaQubits added via .add_bits are added to .qubits."""
anc = AncillaQubit()
qb = Qubit()
qc = QuantumCircuit()
qc.add_bits([anc, qb])
self.assertEqual(qc.qubits, [anc, qb])
def test_dangling_qubits(self):
"""Test that dangling qubits are not allowed."""
loose = [Qubit() for _ in [None] * 5]
reg = QuantumRegister(5)
qc = QuantumCircuit(loose, reg)
message = "Circuit has qubits not contained in the qubit register."
with self.assertRaisesRegex(TranspilerError, message):
Commuting2qGateRouter(self.swap_strat).run(circuit_to_dag(qc))
def test_add_registerless_bits(self):
"""Verify we can add are retrieve bits without an associated register."""
qubits = [Qubit() for _ in range(5)]
clbits = [Clbit() for _ in range(3)]
dag = DAGDependency()
dag.add_qubits(qubits)
dag.add_clbits(clbits)
self.assertEqual(dag.qubits, qubits)
self.assertEqual(dag.clbits, clbits)
def test_addding_individual_bit(self):
"""Verify we can add a single bit to a circuit."""
qr = QuantumRegister(3, "qr")
qc = QuantumCircuit(qr)
new_bit = Qubit()
qc.add_bits([new_bit])
self.assertEqual(qc.qubits, list(qr) + [new_bit])
self.assertEqual(qc.qregs, [qr])
