def test_apply_operation_back_conditional(self):
"""Test consistency of apply_operation_back with condition set."""
# Single qubit gate conditional: qc.h(qr[2]).c_if(cr, 3)
h_gate = HGate()
h_gate.condition = self.condition
h_node = self.dag.apply_operation_back(h_gate, [self.qubit2], [],
h_gate.condition)
self.assertEqual(h_node.qargs, [self.qubit2])
self.assertEqual(h_node.cargs, [])
self.assertEqual(h_node.condition, h_gate.condition)
self.assertEqual(
sorted(self.dag._get_multi_graph_in_edges(h_node._node_id)),
sorted([
(self.dag.input_map[self.qubit2]._node_id, h_node._node_id, {
'wire': self.qubit2,
'name': 'qr[2]'
}),
(self.dag.input_map[self.clbit0]._node_id, h_node._node_id, {
'wire': self.clbit0,
'name': 'cr[0]'
}),
(self.dag.input_map[self.clbit1]._node_id, h_node._node_id, {
'wire': self.clbit1,
'name': 'cr[1]'
}),
]))
self.assertEqual(
sorted(self.dag._get_multi_graph_out_edges(h_node._node_id)),
sorted([
(h_node._node_id, self.dag.output_map[self.qubit2]._node_id, {
'wire': self.qubit2,
'name': 'qr[2]'
}),
(h_node._node_id, self.dag.output_map[self.clbit0]._node_id, {
'wire': self.clbit0,
'name': 'cr[0]'
}),
(h_node._node_id, self.dag.output_map[self.clbit1]._node_id, {
'wire': self.clbit1,
'name': 'cr[1]'
}),
]))
if self.dag._USE_RX:
self.assertTrue(rx.is_directed_acyclic_graph(
self.dag._multi_graph))
else:
self.assertTrue(nx.is_directed_acyclic_graph(
self.dag._multi_graph))
def test_apply_operation_back_conditional(self):
"""Test consistency of apply_operation_back with condition set."""
# Single qubit gate conditional: qc.h(qr[2]).c_if(cr, 3)
h_gate = HGate()
h_gate.condition = self.condition
h_node = self.dag.apply_operation_back(h_gate, [self.qubit2], [],
h_gate.condition)
self.assertEqual(h_node.qargs, [self.qubit2])
self.assertEqual(h_node.cargs, [])
self.assertEqual(h_node.condition, h_gate.condition)
self.assertEqual(
sorted(self.dag._multi_graph.in_edges(h_node, data=True)),
sorted([
(self.dag.input_map[self.qubit2], h_node, {
'wire': Qubit(*self.qubit2),
'name': 'qr[2]'
}),
(self.dag.input_map[self.clbit0], h_node, {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(self.dag.input_map[self.clbit1], h_node, {
'wire': Clbit(*self.clbit1),
'name': 'cr[1]'
}),
]))
self.assertEqual(
sorted(self.dag._multi_graph.out_edges(h_node, data=True)),
sorted([
(h_node, self.dag.output_map[self.qubit2], {
'wire': Qubit(*self.qubit2),
'name': 'qr[2]'
}),
(h_node, self.dag.output_map[self.clbit0], {
'wire': Clbit(*self.clbit0),
'name': 'cr[0]'
}),
(h_node, self.dag.output_map[self.clbit1], {
'wire': Clbit(*self.clbit1),
'name': 'cr[1]'
}),
]))
self.assertTrue(nx.is_directed_acyclic_graph(self.dag._multi_graph))
