def test_layout_combine_bigger(self):
"""combine_into_edge_map() method with another_layout is bigger"""
layout = Layout()
layout.add(self.qr[0])
layout.add(self.qr[1])
another_layout = Layout()
another_layout.add(self.qr[1])
another_layout.add(self.qr[0])
another_layout.add(self.qr[2])
edge_map = layout.combine_into_edge_map(another_layout)
self.assertDictEqual(edge_map, {
(self.qr, 0): (self.qr, 1),
(self.qr, 1): (self.qr, 0)
})
def run(self, dag):
"""Run the ApplyLayout pass on `dag`.
Args:
dag (DAGCircuit): DAG to map.
Returns:
DAGCircuit: A mapped DAG (with physical qubits).
Raises:
TranspilerError: if no layout is found in `property_set` or no full physical qubits.
"""
layout = self.property_set["layout"]
if not layout:
raise TranspilerError(
"No 'layout' is found in property_set. Please run a Layout pass in advance."
)
if len(layout) != (1 + max(layout.get_physical_bits())):
raise TranspilerError("The 'layout' must be full (with ancilla).")
post_layout = self.property_set["post_layout"]
q = QuantumRegister(len(layout), "q")
new_dag = DAGCircuit()
new_dag.add_qreg(q)
new_dag.metadata = dag.metadata
new_dag.add_clbits(dag.clbits)
for creg in dag.cregs.values():
new_dag.add_creg(creg)
if post_layout is None:
for qreg in dag.qregs.values():
self.property_set["layout"].add_register(qreg)
virtual_phsyical_map = layout.get_virtual_bits()
for node in dag.topological_op_nodes():
qargs = [q[virtual_phsyical_map[qarg]] for qarg in node.qargs]
new_dag.apply_operation_back(node.op, qargs, node.cargs)
else:
# First build a new layout object going from:
# old virtual -> old phsyical -> new virtual -> new physical
# to:
# old virtual -> new physical
full_layout = Layout()
old_phys_to_virtual = layout.get_physical_bits()
new_virtual_to_physical = post_layout.get_virtual_bits()
qubit_index_map = {
bit: index
for index, bit in enumerate(dag.qubits)
}
for new_virt, new_phys in new_virtual_to_physical.items():
old_phys = qubit_index_map[new_virt]
old_virt = old_phys_to_virtual[old_phys]
full_layout.add(old_virt, new_phys)
for reg in layout.get_registers():
full_layout.add_register(reg)
# Apply new layout to the circuit
for node in dag.topological_op_nodes():
qargs = [
q[new_virtual_to_physical[qarg]] for qarg in node.qargs
]
new_dag.apply_operation_back(node.op, qargs, node.cargs)
self.property_set["layout"] = full_layout
new_dag._global_phase = dag._global_phase
return new_dag
