def test_design_get_chip_size(self):
"""
Test getting chip size in design_base.py.
"""
design = DesignPlanar(metadata={})
main_expected = {
'center_x': '0.0mm',
'center_y': '0.0mm',
'center_z': '0.0mm',
'size_x': '9mm',
'size_y': '6mm',
'size_z': '-750um',
'sample_holder_top': '890um',
'sample_holder_bottom': '1650um'
}
self.assertEqual(design.get_chip_size(), main_expected)
self.assertEqual(design.get_chip_size('main'), main_expected)
self.assertEqual(design.get_chip_size('dead'), {})
def test_design_qnet_delete_net_id(self):
"""Test delete a given net id in net_info.py."""
design = DesignPlanar(metadata={})
QComponent(design, 'my_name-1', make=False)
QComponent(design, 'my_name-2', make=False)
Components(design)
qnet = QNet()
net_id = qnet.add_pins_to_table(1, 'my_name-1', 2, 'my_name-2')
qnet.delete_net_id(net_id)
df = qnet.net_info
self.assertEqual(df.empty, True)
def test_design_interface_components_find_id(self):
"""
Test finding the id from the name in interface_components.py.
"""
design = DesignPlanar(metadata={})
QComponent(design, 'my_name-1', make=False)
QComponent(design, 'my_name-2', make=False)
components = Components(design)
self.assertEqual(components.find_id('my_name-1'), 1)
self.assertEqual(components.find_id('my_name-2'), 2)
self.assertEqual(components.find_id('my_name-3'), 0)
def test_design_get_and_set_design_name(self):
"""Test getting the design name in design_base.py."""
design = DesignPlanar(metadata={})
self.assertEqual(design.get_design_name(), 'my_design')
design.set_design_name('new-name')
self.assertEqual(design.get_design_name(), 'new-name')
def test_design_interface_components_get_list_ints(self):
"""Test geting the list ints in interface_components.py."""
design = DesignPlanar(metadata={})
QComponent(design, 'my_name-1', make=False)
QComponent(design, 'my_name-2', make=False)
components = Components(design)
self.assertListEqual(components.get_list_ints(['my_name-1']), [1])
self.assertListEqual(
components.get_list_ints(['my_name-1', 'my_name-2']), [1, 2])
self.assertListEqual(
components.get_list_ints(['my_name-1', 'my_name-2', 'nope']),
[1, 2, 0])
def test_design_rename_variables(self):
"""Test variable renaming in design_base.py."""
design = DesignPlanar(metadata={})
design.rename_variable('cpw_gap', 'new-name')
with self.assertRaises(ValueError):
design.rename_variable('i-do-not-exist', 'uh-oh')
self.assertEqual('new-name' in design.variables.keys(), True)
self.assertEqual('cpw_gap' in design.variables.keys(), False)
def test_design_delete_all_pins(self):
"""Test delete_all_pins functionality in design_base.py."""
design = DesignPlanar()
design.overwrite_enabled = True
TransmonPocket(design, 'Q1')
TransmonPocket(design, 'Q2')
design.connect_pins(1, 'p1', 2, 'p2')
pf = design._qnet._net_info
self.assertFalse(pf.empty)
design.delete_all_pins()
pf = design._qnet._net_info
self.assertTrue(pf.empty)
def test_design_update_metadata(self):
"""Test the update of metadata in design_base.py."""
design = DesignPlanar(metadata={})
data = design.metadata
design.update_metadata({'new-key': 'new-value'})
design.update_metadata({'time_created': '07/23/2020, 17:00:00'})
data = design.metadata
self.assertEqual(len(data), 4)
self.assertEqual(data['design_name'], 'my_design')
self.assertEqual(data['notes'], '')
self.assertEqual(data['time_created'], '07/23/2020, 17:00:00')
self.assertEqual(data['new-key'], 'new-value')
def test_design_get_list_of_tables_in_metadata(self):
"""Tests the get_list_of_tables_in_metadata function in design_base.py
by exeucting get_table_values_form_renderers in a component."""
design = DesignPlanar()
q1 = TransmonPocket(design, 'Q1')
result = q1._get_table_values_from_renderers(design)
self.assertEqual(len(result), 11)
self.assertEqual(result['hfss_inductance'], '10nH')
self.assertEqual(result['hfss_capacitance'], 0)
self.assertEqual(result['hfss_resistance'], 0)
self.assertAlmostEqual(result['hfss_mesh_kw_jj'], 7e-06, places=6)
self.assertEqual(result['q3d_inductance'], '10nH')
self.assertEqual(result['q3d_capacitance'], 0)
self.assertEqual(result['q3d_resistance'], 0)
self.assertAlmostEqual(result['q3d_mesh_kw_jj'], 7e-06, places=6)
self.assertEqual(result['gds_cell_name'], 'my_other_junction')
self.assertEqual(result['hfss_wire_bonds'], False)
self.assertEqual(result['q3d_wire_bonds'], False)
def test_design_qnet_get_components_and_pins_for_netid(self):
"""
Test get_components_Sand_pins_for_netid in net_info.py.
"""
design = DesignPlanar(metadata={})
QComponent(design, 'my_name-1', make=False)
QComponent(design, 'my_name-2', make=False)
QComponent(design, 'my_name-3', make=False)
QComponent(design, 'my_name-4', make=False)
Components(design)
qnet = QNet()
net_id_1 = qnet.add_pins_to_table(1, 'my_name-1', 2, 'my_name-2')
net_id_2 = qnet.add_pins_to_table(3, 'my_name-3', 4, 'my_name-4')
data = {
'net_id': [1, 1],
'component_id': [1, 2],
'pin_name': ['my_name-1', 'my_name-2']
}
df_expected_1 = pd.DataFrame(data, index=[0, 1])
data = {
'net_id': [2, 2],
'component_id': [3, 4],
'pin_name': ['my_name-3', 'my_name-4']
}
df_expected_2 = pd.DataFrame(data, index=[2, 3])
df = qnet.get_components_and_pins_for_netid(net_id_1)
self.assertEqual(len(df), len(df_expected_1))
data_points = df_expected_1['net_id'].size
for i in range(data_points):
for j in ['net_id', 'component_id', 'pin_name']:
self.assertEqual(df_expected_1[j][i], df[j][i])
df = qnet.get_components_and_pins_for_netid(net_id_2)
self.assertEqual(len(df), len(df_expected_2))
for i in [2, 3]:
for j in ['net_id', 'component_id', 'pin_name']:
self.assertEqual(df_expected_2[j][i], df[j][i])
def test_design_default_component_name(self):
"""Test automatic naming of components."""
design = DesignPlanar(metadata={})
ResonatorCoilRect(design, make=False)
self.assertEqual('res_1' in design.components, True)
ResonatorCoilRect(design, make=False)
self.assertEqual('res_2' in design.components, True)
# Manually add the next automatic name to check it doesn't get repeated
ResonatorCoilRect(design, 'res_3', make=False)
ResonatorCoilRect(design, make=False)
self.assertEqual('res_3' in design.components, True)
self.assertEqual('res_4' in design.components, True)
# Add a different component
TransmonPocket(design, make=False)
self.assertEqual('Q_1' in design.components, False)
# Add a component with no predefined prefix
QComponent(design, make=False)
self.assertEqual('QComponent_1' in design.components, True)
def test_design_qnet_add_pins_to_table(self):
"""Test add_pins_to_table in net_info.py."""
design = DesignPlanar(metadata={})
QComponent(design, 'my_name-1', make=False)
QComponent(design, 'my_name-2', make=False)
Components(design)
qnet = QNet()
qnet.add_pins_to_table(1, 'my_name-1', 2, 'my_name-2')
df = qnet.net_info
data = {
'net_id': [1, 1],
'component_id': [1, 2],
'pin_name': ['my_name-1', 'my_name-2']
}
df_expected = pd.DataFrame(data, index=[0, 1])
self.assertEqual(len(df), len(df_expected))
data_points = df_expected['net_id'].size
for i in range(data_points):
for j in ['net_id', 'component_id', 'pin_name']:
self.assertEqual(df_expected[j][i], df[j][i])
def test_design_get_units(self):
"""Test get units in design_base.py."""
design = DesignPlanar(metadata={})
self.assertEqual(design.get_units(), 'mm')
def test_design_get_chip_z(self):
"""Test getting chip z in design_base.py."""
design = DesignPlanar(metadata={})
actual = design.get_chip_z()
self.assertEqual(actual, '0.0mm')
