def generate_top_ral(top, ip_objs, out_path): # construct top ral block top_block = gen_rtl.Block() top_block.name = "chip" top_block.base_addr = 0 top_block.width = int(top["datawidth"]) # add blocks for ip_obj in ip_objs: top_block.blocks.append(gen_rtl.json_to_reg(ip_obj)) # add memories if "memory" in top.keys(): for item in list(top["memory"]): mem = gen_rtl.Window() mem.name = item["name"] mem.base_addr = int(item["base_addr"], 0) mem.limit_addr = int(item["base_addr"], 0) + int(item["size"], 0) # TODO: need to add mem access info for memories in topcfg mem.dvrights = "RW" mem.n_bits = top_block.width top_block.wins.append(mem) # get sub-block base addresses from top cfg for block in top_block.blocks: for module in top["module"]: if block.name == module["name"]: block.base_addr = module["base_addr"] break top_block.blocks.sort(key=lambda block: block.base_addr) top_block.wins.sort(key=lambda win: win.base_addr) # generate the top ral model with template gen_dv.gen_ral(top_block, str(out_path))
def generate_top_ral(top, ip_objs, dv_base_prefix, out_path): # construct top ral block top_block = gen_rtl.Block() top_block.name = "chip" top_block.base_addr = 0 top_block.width = int(top["datawidth"]) # add all the IPs into blocks for ip_obj in ip_objs: top_block.blocks.append(gen_rtl.json_to_reg(ip_obj)) assert top_block.width % 8 == 0 reg_width_in_bytes = top_block.width // 8 # add memories for item in list(top.get("memory", [])): byte_write = ('byte_write' in item and item["byte_write"].lower() == "true") size_in_bytes = int(item['size'], 0) num_regs = size_in_bytes // reg_width_in_bytes swaccess = access.SWAccess('top-level memory', item.get('swaccess', 'rw')) mem = window.Window(name=item['name'], desc='(generated from top-level)', unusual=False, byte_write=byte_write, validbits=top_block.width, items=num_regs, size_in_bytes=size_in_bytes, offset=int(item["base_addr"], 0), swaccess=swaccess) top_block.wins.append(mem) # get sub-block base addresses, instance names from top cfg for block in top_block.blocks: for module in top["module"]: if block.name == module["type"]: block.base_addr[module["name"]] = int(module["base_addr"], 0) # sort by the base_addr of 1st instance of the block top_block.blocks.sort(key=lambda block: next(iter(block.base_addr))[1]) top_block.wins.sort(key=lambda win: win.offset) # generate the top ral model with template gen_dv.gen_ral(top_block, dv_base_prefix, str(out_path))
def generate_top_ral(top, ip_objs, dv_base_prefix, out_path): # construct top ral block regwidth = int(top['datawidth']) assert regwidth % 8 == 0 addrsep = regwidth // 8 # Get sub-block base addresses and instance names from top cfg sub_blocks = {} # type: Dict[int, Tuple[str, IpBlock]] for block in ip_objs: block_lname = block.name.lower() for module in top["module"]: if block_lname == module["type"]: block_addr = int(module["base_addr"], 0) assert block_addr not in sub_blocks sub_blocks[block_addr] = (module["name"], block) # Collect up the memories to add mems = [] for item in list(top.get("memory", [])): byte_write = ('byte_write' in item and item["byte_write"].lower() == "true") size_in_bytes = int(item['size'], 0) num_regs = size_in_bytes // addrsep swaccess = access.SWAccess('top-level memory', item.get('swaccess', 'rw')) mems.append( window.Window(name=item['name'], desc='(generated from top-level)', unusual=False, byte_write=byte_write, validbits=regwidth, items=num_regs, size_in_bytes=size_in_bytes, offset=int(item["base_addr"], 0), swaccess=swaccess)) chip = Top(regwidth, sub_blocks, mems) # generate the top ral model with template gen_dv.gen_ral(chip, dv_base_prefix, str(out_path))
def generate_top_ral(top, ip_objs, dv_base_prefix, out_path): # construct top ral block top_block = gen_rtl.Block() top_block.name = "chip" top_block.base_addr = 0 top_block.width = int(top["datawidth"]) # add all the IPs into blocks for ip_obj in ip_objs: top_block.blocks.append(gen_rtl.json_to_reg(ip_obj)) # add memories if "memory" in top.keys(): for item in list(top["memory"]): mem = gen_rtl.Window() mem.name = item["name"] mem.base_addr = int(item["base_addr"], 0) mem.limit_addr = int(item["base_addr"], 0) + int(item["size"], 0) mem.byte_write = ('byte_write' in item and item["byte_write"].lower() == "true") if "swaccess" in item.keys(): mem.dvrights = item["swaccess"] else: mem.dvrights = "RW" mem.n_bits = top_block.width top_block.wins.append(mem) # get sub-block base addresses, instance names from top cfg for block in top_block.blocks: for module in top["module"]: if block.name == module["type"]: block.base_addr[module["name"]] = int(module["base_addr"], 0) # sort by the base_addr of 1st instance of the block top_block.blocks.sort(key=lambda block: next(iter(block.base_addr))[1]) top_block.wins.sort(key=lambda win: win.base_addr) # generate the top ral model with template gen_dv.gen_ral(top_block, dv_base_prefix, str(out_path))