class c_clock_timer_test_master_slave_7(c_clock_timer_test_master_slave_base): (slave_adder, slave_bonus) = clock_timer_adder_bonus(100.0) slave_lock = True master_sync = 0xdeadbeefcafef00d lock_window_lsb = 10 max_diff = 100 # 10MHz pass
class c_clock_timer_test_master_slave_5(c_clock_timer_test_master_slave_base): (slave_adder, slave_bonus) = clock_timer_adder_bonus(10.0) slave_lock = True master_sync = ((10**9)*0xfeedbeee) - 1000 lock_window_lsb = 6 max_diff = 10 # 100MHz pass
class c_clock_timer_test_master_slave_4(c_clock_timer_test_master_slave_base): (slave_adder, slave_bonus) = clock_timer_adder_bonus(1.599) slave_lock = True master_sync = ((10**9)*0xfeedbeef) - 1000 lock_window_lsb = 4 max_diff = 2 # 600MHz pass
class c_clock_timer_test_master_slave_6(c_clock_timer_test_master_slave_base): (slave_adder, slave_bonus) = clock_timer_adder_bonus(100.1) slave_lock = True master_sync = 0xdeadbeefcafef00d lock_window_lsb = 8 max_diff = 100 # 10MHz # In theory this may not work - as the edge detection is too frequent # And indeed it does not, except that we have oversped the clock by 1/1600 # and this helps catch up with the initial delay in synchronization pass
class c_clock_timer_test_base(ThExecFile): """ Find a slightly slower bonus fraction for 1.6ns """ master_adder = (1,0) master_bonus = (0,0) (slave_adder, slave_bonus) = clock_timer_adder_bonus(1.6) slave_lock = False lock_window_lsb = 6 hw_clk = "clk" #f configure_master def configure_master(self, adder, bonus=(0,0)): self.master_timer_control__bonus_subfraction_sub.drive(bonus[1]) self.master_timer_control__bonus_subfraction_add.drive(bonus[0]) self.master_timer_control__fractional_adder.drive(adder[1]) self.master_timer_control__integer_adder.drive(adder[0]) self.master_timer_control__reset_counter.drive(1) self.master_timer_control__enable_counter.drive(0) print("Master configured for %fns %fMHz"%(clock_timer_period(adder, bonus),1000.0/clock_timer_period(adder, bonus))) pass #f configure_slave def configure_slave(self, adder, bonus=(0,0), lock=False): self.slave_timer_control__bonus_subfraction_sub.drive(bonus[1]) self.slave_timer_control__bonus_subfraction_add.drive(bonus[0]) self.slave_timer_control__fractional_adder.drive(adder[1]) self.slave_timer_control__integer_adder.drive(adder[0]) self.slave_timer_control__reset_counter.drive(1) self.slave_timer_control__enable_counter.drive(0) print("Slave configured for %fns %fMHz"%(clock_timer_period(adder, bonus),1000.0/clock_timer_period(adder, bonus))) if lock: self.master_timer_control__lock_to_master.drive(1) self.master_timer_control__lock_window_lsb.drive({4:0,6:1,8:2,10:3}[self.lock_window_lsb]) pass else: self.master_timer_control__lock_to_master.drive(0) pass pass pass
class c_clock_timer_test_master_slave_3(c_clock_timer_test_master_slave_base): (slave_adder, slave_bonus) = clock_timer_adder_bonus(1.599) slave_lock = True lock_window_lsb = 4 max_diff = 2 # 600MHz pass