# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # # Authors: Steve Reinhardt import m5 from m5.objects import * m5.util.addToPath('../configs/common') m5.util.addToPath('../configs/topologies') import ruby_config ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", 1) cpu = DerivO3CPU(cpu_id=0) cpu.clock = '2GHz' system = System(cpu = cpu, physmem = ruby_memory, membus = CoherentBus(), mem_mode = "timing") system.physmem.port = system.membus.master # create the interrupt controller cpu.createInterruptController() cpu.connectAllPorts(system.membus) # Connect the system port for loading of binaries etc system.system_port = system.membus.slave
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. import m5 from m5.objects import * nb_cores = 4 cpus = [DerivO3CPU(cpu_id=i) for i in range(nb_cores)] import ruby_config ruby_memory = ruby_config.generate("TwoLevel_SplitL1UnifiedL2.rb", nb_cores) # system simulated system = System(cpu=cpus, physmem=ruby_memory, membus=SystemXBar(), mem_mode="timing", clk_domain=SrcClockDomain(clock='1GHz')) # Create a seperate clock domain for components that should run at # CPUs frequency system.cpu_clk_domain = SrcClockDomain(clock='2GHz') for cpu in cpus: # create the interrupt controller cpu.createInterruptController()