def dependencies(filename): schem = schematic.Schematic(open(filename)) devices = set(c.device for c in schem.findall(type="component", attr="device=") if c.device not in ["none", "IPAD", "OPAD", "IOPAD"]) if filename != CLOCK_SCH_FILENAME: devices |= dependencies(CLOCK_SCH_FILENAME) return devices
def slot_count(device, _cache={}): if device in _cache: return _cache[device] filename = os.path.join(SYMBOL_PATH, device + "-1.sym") schem = schematic.Schematic(open(filename)) attr = next(schem.findall(text="numslots")) slots = int(attr["text"].split("=")[-1]) _cache[device] = slots return slots
def main(args): if len(args) != 2: print("USAGE: %s module.sch output.sch" % sys.argv[0]) print("Updates schemtic wires from X0 to X[0] to facilitate netlisting") return 2 filename = args[0] schem = schematic.Schematic(open(filename)) fix_wires(schem, filename) fix_busses(schem, filename) add_title_block(schem, filename) schem.save(open(args[1], "w"))
def main(args): try: if len(args) < 2: print("USAGE: %s module.v module.sch [module2.sch...]" % (sys.argv[0])) print("Fixes netlisted verilog code") return 2 filename = args[0] schems = [ schematic.Schematic(f) for f in (open(arg) for arg in args[1:]) ] modname = os.path.basename(filename[:-2]) out_stream = io.StringIO() with open(filename) as in_stream: fixup(in_stream, out_stream, modname, schems) out_stream.seek(0) with open(filename, "w") as new_stream: for data in out_stream: new_stream.write(data) except NetlistException as e: print("ERROR: %s {%s}" % (str(e), " ".join(args))) return 1
def main(args): if not args: print("USAGE: %s [--overwrite] schem.sch [..schem.sch]" % sys.argv[0]) print("Renames all U? refdes found in schematics.") print(" --overwrite renames all refdes") return 2 overwrite = False if args[0] == "--overwrite": overwrite = True args = args[1:] schems = [schematic.Schematic(f) for f in (open(fn) for fn in args)] all_components = [components(s) for s in schems] if overwrite: rename = [list(filter(refdes_set, cs)) for cs in all_components] named = [] else: rename = [list(filter(refdes_blank, cs)) for cs in all_components] named = flatten(list(filter(refdes_set, cs)) for cs in all_components) seq = refdes_sequence(named) for i, comps in enumerate(rename): set_refdes(comps, seq) for schem, filename in zip(schems, args): schem.save(open(filename, "w"))
def test_column_type_from_name_raises_notimplemented_base(self): with self.assertRaises(NotImplementedError): schematic.Schematic().column_type_from_name("dummy")
def test_get_type_raises_valueerror_for_base(self): with self.assertRaises(ValueError): schematic.Schematic().get_type("dummy")