def net(self, name, drive=skidl.Pin.NO_DRIVE):
''' define or return a well-known net '''
if name in self._nets:
return self._nets[name]
net = skidl.Net(name, circuit=self.circuit)
net.drive = drive
self._nets[name] = net
return net
def circuit(self, port):
circuit_nets = {}
gnd = skidl.Net('GND')
decoupling_caps = []
fpga = skidl.Part(lib=altera_sklib.altera,
name='10M02SCE',
footprint='EQFP144')
#Power related pins
for pin in fpga.pins:
if "GND" in pin.name:
pin += gnd
elif "VCC" in pin.name:
if pin.name not in circuit_nets.keys():
circuit_nets[pin.name] = skidl.Net(pin.name)
decoupling_caps.append(
skidl.Part('device',
'C',
value='100n',
footprint='Capacitors_SMD:C_0805'))
pin += circuit_nets[pin.name]
decoupling_caps[-1][1] += circuit_nets[pin.name]
decoupling_caps[-1][2] += gnd
def create_nets(top):
nets = {}
nets['0']=GND
nets['1']=VCC
for name, net in top['netnames'].items():
for bit in net['bits']:
if not bit in nets:
net = skidl.Net(name)
nets[bit] = net
else:
net = nets[bit]
# suppress ERC warnings about unconnected pins
if name in top['ports'] and top['ports'][name]['direction']=='input':
net.drive = skidl.POWER
return nets
#!/usr/bin/python
import skidl
skidl.lib_search_paths[skidl.KICAD].append('gsg-kicad-lib')
gnd = skidl.Net('GND')
vcc = skidl.Net('VCC')
num_leds = 242
leds = []
sdi = []
cki = []
for i in range(num_leds):
leds.append(
skidl.Part('gsg-symbols.lib',
'APA102',
footprint='gsg-modules:APA102-2020'))
sdi.append(skidl.Net('SDI' + str(i)))
cki.append(skidl.Net('SDO' + str(i)))
leds[i]['SDI'] += sdi[i]
leds[i]['CKI'] += cki[i]
leds[i]['GND'] += gnd
leds[i]['VCC'] += vcc
# connect input to previous output
if 0 < i:
leds[i - 1]['SDO'] += sdi[i]
leds[i - 1]['CKO'] += cki[i]
# don't connect the output of the last LED
leds[-1]['SDO'] += NC
import skidl
# create KiCad nets
VCC = skidl.Net('VCC')
VCC.drive = skidl.POWER
GND = skidl.Net('GND')
GND.drive = skidl.POWER
def new_cap():
"a decoupling capacitor"
chip = skidl.Part('Device', 'C', footprint="Capacitor_THT:C_Disc_D4.7mm_W2.5mm_P5.00mm")
chip[1] += VCC
chip[2] += GND
def new_74374():
"8-bit DFF"
chip = skidl.Part('74xx', '74LS374', footprint="Package_DIP:DIP-20_W7.62mm")
chip.VCC += VCC
chip.GND += GND
chip.OE += GND # enable
return chip
def new_74377():
"8-bit DFFE"
chip = skidl.Part('74xx', '74LS377', footprint="Package_DIP:DIP-20_W7.62mm")
chip.VCC += VCC
chip.GND += GND
return chip
def new_74244():
"8-bit buffer"
#!/usr/bin/python
import skidl
skidl.lib_search_paths[skidl.KICAD].append('gsg-kicad-lib')
gnd = skidl.Net('GND')
vcc = skidl.Net('VCC')
num_leds = 242
leds = []
sdo = []
cko = []
for i in range(num_leds):
leds.append(
skidl.Part('gsg-symbols.lib',
'APA102',
footprint='gsg-modules:APA102-2020'))
sdo.append(skidl.Net('SDO' + str(i)))
cko.append(skidl.Net('CKO' + str(i)))
leds[i]['SDI'] += sdo[i]
leds[i]['CKI'] += cko[i]
leds[i]['GND'] += gnd
leds[i]['VCC'] += vcc
# connect input to previous output
if 0 < i:
leds[i - 1]['SDO'] += sdo[i]
leds[i - 1]['CKO'] += cko[i]
# don't connect the output of the last LED
leds[-1]['SDO'] += NC