def process_array_type(typ):
'''
Takes an array type produced by 'inner_vhdl_parser' and returns one from'typs'.
'''
subtype_mark = typ.subtype_indication.type_mark
if typ.subtype_indication.constraint:
size = get_constraint_size(typ.subtype_indication.constraint)
subtype = typs.UnresolvedConstrainedArray(
identifier=None,
size=size,
unconstrained_type_identifier=subtype_mark)
subtype_identifier = None
else:
subtype = None
subtype_identifier = subtype_mark
size = get_size(typ)
if size is None:
processed = typs.UnresolvedArray(
identifier=typ.identifier,
subtype_identifier=subtype_identifier,
subtype=subtype,
)
else:
unconstrained = typs.UnresolvedArray(
identifier=None,
subtype_identifier=subtype_identifier,
subtype=subtype,
)
processed = typs.UnresolvedConstrainedArray(
identifier=typ.identifier,
unconstrained_type=unconstrained,
size=size,
)
return processed
def process_array_type(typ):
subtype_mark = typ.subtype_indication.type_mark
if typ.subtype_indication.constraint:
size = get_constraint_size(typ.subtype_indication.constraint)
subtype = typs.UnresolvedConstrainedArray(
identifier=None,
size=size,
unconstrained_type_identifier=subtype_mark)
subtype_identifier = None
else:
subtype = None
subtype_identifier = subtype_mark
size = get_size(typ)
if size is None:
processed = typs.UnresolvedArray(
identifier=typ.identifier,
subtype_identifier=subtype_identifier,
subtype=subtype,
)
else:
unconstrained = typs.UnresolvedArray(
identifier=None,
subtype_identifier=subtype_identifier,
subtype=subtype,
)
processed = typs.UnresolvedConstrainedArray(
identifier=typ.identifier,
unconstrained_type=unconstrained,
size=size,
)
return processed
def process_subtype_indication(subtype_indication):
'''
Takes an array type produced by 'inner_vhdl_parser' and returns one from'typs'.
'''
constraint = subtype_indication.constraint
type_mark = subtype_indication.type_mark
if constraint:
size = get_constraint_size(constraint)
else:
size = None
if (not constraint):
subtype = type_mark
else:
if type_mark == 'std_logic_vector':
subtype = typs.UnresolvedConstrainedStdLogicVector(
identifier=None,
size=size,
)
elif type_mark == 'unsigned':
subtype = typs.UnresolvedConstrainedUnsigned(
identifier=None,
size=size,
)
elif type_mark == 'signed':
subtype = typs.UnresolvedConstrainedSigned(
identifier=None,
size=size,
)
else:
subtype = typs.UnresolvedConstrainedArray(
identifier=None,
unconstrained_type_identifier=type_mark,
size=size,
)
return subtype
def process_subtype(typ):
'''
Takes a type produced by 'inner_vhdl_parser' and returns one from 'typs'.
'''
subtype_mark = typ.subtype_indication.type_mark
size = get_size(typ)
if size is None:
# Failed to process subtype.
processed = None
else:
if subtype_mark == 'std_logic_vector':
processed = typs.UnresolvedConstrainedStdLogicVector(
identifier=typ.identifier,
size=size,
)
elif subtype_mark == 'unsigned':
processed = typs.UnresolvedConstrainedUnsigned(
identifier=typ.identifier,
size=size,
)
elif subtype_mark == 'signed':
processed = typs.UnresolvedConstrainedSigned(
identifier=typ.identifier,
size=size,
)
else:
processed = typs.UnresolvedConstrainedArray(
identifier=typ.identifier,
unconstrained_type_identifier=subtype_mark,
size=size,
)
return processed
def process_subtype_indication(subtype_indication):
constraint = subtype_indication.constraint
type_mark = subtype_indication.type_mark
if constraint:
size = get_constraint_size(constraint)
else:
size = None
if (not constraint):
subtype = type_mark
else:
if type_mark == 'std_logic_vector':
subtype = typs.UnresolvedConstrainedStdLogicVector(
identifier=None,
size=size,
)
elif type_mark == 'unsigned':
subtype = typs.UnresolvedConstrainedUnsigned(
identifier=None,
size=size,
)
elif type_mark == 'signed':
subtype = typs.UnresolvedConstrainedSigned(
identifier=None,
size=size,
)
else:
subtype = typs.UnresolvedConstrainedArray(
identifier=None,
unconstrained_type_identifier=type_mark,
size=size,
)
return subtype
def process_subtype(typ):
subtype_mark = typ.subtype_indication.type_mark
size = get_size(typ)
if size is None:
# Failed to process subtype.
processed = None
else:
if subtype_mark == 'std_logic_vector':
processed = typs.UnresolvedConstrainedStdLogicVector(
identifier=typ.identifier,
size=size,
)
elif subtype_mark == 'unsigned':
processed = typs.UnresolvedConstrainedUnsigned(
identifier=typ.identifier,
size=size,
)
elif subtype_mark == 'signed':
processed = typs.UnresolvedConstrainedSigned(
identifier=typ.identifier,
size=size,
)
else:
processed = typs.UnresolvedConstrainedArray(
identifier=typ.identifier,
unconstrained_type_identifier=subtype_mark,
size=size,
)
return processed