def __init__(self, dfml_hwm):
self.ran = False
self.dfml_hwm = dfml_hwm
self.hwm = DfMuxWiringMap()
for ch in self.dfml_hwm.channels:
bolo_id = str(self.dfml_hwm(ch, 'channel_id'))
if self.dfml_hwm(ch, 'bolo_id') == '':
# Check bolo_id, which is set iff this is a channel we care about
continue
mapping = DfMuxChannelMapping()
mapping.board_ip = struct.unpack("i", socket.inet_aton( self.dfml_hwm(ch, 'dfmux_ip') ))[0]
mapping.board_serial = int(self.dfml_hwm(ch, 'dfmux_id'))
if self.dfml_hwm(ch, 'crate_slot') is not None:
mapping.board_slot = int(self.dfml_hwm(ch, 'crate_slot'))
mapping.crate_serial = -1
mapping.module = self.dfml_hwm(ch, 'module') - 1
mapping.channel = self.dfml_hwm(ch, 'chan_num') - 1
self.hwm[bolo_id] = mapping
def __init__(self, pydfmux_hwm, pathstring=None, state=[]):
self.ran = False
from pydfmux.core import dfmux as pydfmux
self.hwmf = core.G3Frame(core.G3FrameType.Wiring)
hwm = DfMuxWiringMap()
if pathstring:
chan_map_query = pydfmux_hwm.channel_maps_from_pstring(pathstring)
else:
chan_map_query = pydfmux_hwm.query(pydfmux.ChannelMapping)
if len(state) > 0:
for bolo in pydfmux_hwm.query(pydfmux.Bolometer):
if bolo.readout_channel:
bolo.state = bolo.retrieve_bolo_state().state
pydfmux_hwm.commit()
chan_map_query = chan_map_query.join(
pydfmux.ChannelMapping,
pydfmux.Bolometer).filter(pydfmux.Bolometer.state._in(state))
for bolo in chan_map_query:
mapping = DfMuxChannelMapping()
mapping.board_ip = struct.unpack(
"i",
socket.inet_aton(
socket.gethostbyname('iceboard' +
str(bolo.iceboard.serial) +
'.local')))[0]
mapping.board_serial = int(bolo.iceboard.serial)
mapping.board_slot = bolo.iceboard.slot if bolo.iceboard.slot else -1
mapping.crate_serial = int(
bolo.iceboard.crate.serial) if bolo.iceboard.slot else -1
mapping.module = bolo.readout_channel.module.module - 1 # pydfmux HWMs use 1-indexing of modules, while FPGA uses 0-indexing
if bolo.readout_channel.mezzanine.mezzanine == 2:
mapping.module += 4
mapping.channel = bolo.readout_channel.channel - 1 # pydfmux HWMs use 1-indexing of channels, while FPGA uses 0-indexing
hwm[str(bolo.bolometer.global_name)] = mapping
self.hwmf['WiringMap'] = hwm
self.hwmf['ReadoutSystem'] = 'ICE'
def __call__(self, frame):
if self.ran:
return frame
from pydfmux.core import dfmux as pydfmux
hwmf = core.G3Frame(core.G3FrameType.Wiring)
hwm = DfMuxWiringMap()
for mod in self.hwm.query(pydfmux.ReadoutModule):
for bolo in range(self.channels):
mapping = DfMuxChannelMapping()
mapping.board_ip = struct.unpack("i", socket.inet_aton(socket.gethostbyname('iceboard' + str(mod.iceboard.serial) + '.local')))[0]
mapping.board_serial = int(mod.iceboard.serial)
mapping.board_slot = mod.iceboard.slot if mod.iceboard.slot else -1
mapping.crate_serial = int(mod.iceboard.crate.serial) if mod.iceboard.slot else -1
mezz = mod.mezzanine.mezzanine
# pydfmux HWMs use 1-indexing of modules, while FPGA uses 0-indexing
mapping.module = (mezz - 1) * NUM_MODS_PER_MEZZ + mod.module - 1
mapping.channel = bolo
hwm[str(mapping)] = mapping
hwmf['WiringMap'] = hwm
hwmf['ReadoutSystem'] = 'ICE'
self.ran = True
return [hwmf, frame]