definition_clean_up(def_to_copy) return definition_copies def clean(definition): for child in definition.children: if child.reference in definition_copies: make_instances_unique(child) definition_count = dict() original_inner_pin_to_new_inner_pin = dict() instance_map = dict() outer_pin_map = dict() definition_copies = dict() example_name = 'unique_challenge' ir = sdn.load_example_netlist_by_name(example_name) top_def = ir.top_instance.reference reverse_topological_order = get_reverse_topological_order(ir) for definition in reverse_topological_order: make_definition_copies(definition, definition_count[definition] - 1) clean(top_def) import tempfile import os with tempfile.TemporaryDirectory() as td: file_name = example_name + '_unique.edf' sdn.compose(ir, os.path.join(td, file_name))
top_wires_sw[i].connect_pin(top_pins_sw[i]) top_wires_sw[i].connect_pin(instance.pins[IBUF_pin_input]) # connect output of sw_IBUF's to input of basic LUT top_cables_sw_IBUF = top_def.create_cable(name="sw_IBUF") top_wires_sw_IBUF = top_cables_sw_IBUF.create_wires(LUT_SIZE) for IBUF_inst, my_LUT_pin, i in zip(top_sw_IBUF_inst_list, my_LUT_pin_input_list, range(LUT_SIZE)): top_wires_sw_IBUF[i].connect_pin(IBUF_inst.pins[IBUF_pin_output]) top_wires_sw_IBUF[i].connect_pin(my_LUT_inst.pins[my_LUT_pin]) # connect output of basic LUT to input of led_OBUF top_cable_led_OBUF = top_def.create_cable(name="led_OBUF") top_wire_led_OBUF = top_cable_led_OBUF.create_wire() top_wire_led_OBUF.connect_pin(top_led_OBUF_inst.pins[OBUF_pin_input]) top_wire_led_OBUF.connect_pin(my_LUT_inst.pins[my_LUT_pin_output]) # connect output of led_OBUF to led top_led_cable = top_def.create_cable(name="led") top_led_wire = top_led_cable.create_wire() top_pin_led = top_port_led.create_pin() top_led_wire.connect_pin(top_led_OBUF_inst.pins[OBUF_pin_output]) top_led_wire.connect_pin(top_pin_led) netlist.set_top_instance(top_def, instance_name=top_def.name) sdn.compose(netlist, "my_LUT.edf")
The netlist example that is loaded in has a LUT configured to be an AND gate, but with SpyDrNet, you can modify that LUT to be something else. The LUT configuration ``'4'h8'`` (an AND gate) for the LUT in the netlist will be changed to ``'4'hE'`` (an OR gate) in this example. After making this configuration, the new netlist will be composed twice, showing that SpyDrNet can either create an EDIF netlist file or a Verilog netlist file that both represent the same netlist. """ import spydrnet as sdn # Change this line to change the configuration of the LUT in the design. LUT_CONFIG = 0xE logic_gate_netlist = sdn.load_example_netlist_by_name("AND_gate") # Alternatively you can parse in your own netlist by changing the line below. # logic_gate_netlist = sdn.parse('<my_netlist.edf>') # Find the LUT2 definition for definition in logic_gate_netlist.get_definitions(): if definition.name == "LUT2": lut_instances = definition.references # Once the LUT2 definition has been found, go through its instances for instance in lut_instances: properties = instance["EDIF.properties"] # Change the value in the properties of the LUT2 instance properties[0]["value"] = "4'h" + str(hex(LUT_CONFIG)).upper()[2:] # The netlist is composed into both an EDIF file and also in a Verliog file sdn.compose(logic_gate_netlist, "OR_gate.edf") sdn.compose(logic_gate_netlist, "OR_gate.v")
def_or2 = library.create_definition(name='OR2') port_or2_a = def_or2.create_port(name='A', direction=sdn.IN) port_or2_b = def_or2.create_port(name='B', direction=sdn.IN) port_or2_q = def_or2.create_port(name='Q', direction=sdn.OUT) pin_or2_a = port_or2_a.create_pin() pin_or2_b = port_or2_b.create_pin() pin_or2_q = port_or2_q.create_pin() # create an instance of OR2 which resides in widget inst_or2 = def_widget.create_child(name='or2', reference=def_or2) # connect all the pins wire_a.connect_pin(pin_widget_a) wire_a.connect_pin(inst_and2_1.pins[pin_and2_a]) wire_b.connect_pin(pin_widget_b) wire_b.connect_pin(inst_and2_1.pins[pin_and2_b]) wire_q_1.connect_pin(inst_and2_1.pins[pin_and2_q]) wire_c.connect_pin(pin_widget_c) wire_c.connect_pin(inst_and2_2.pins[pin_and2_a]) wire_d.connect_pin(pin_widget_d) wire_d.connect_pin(inst_and2_2.pins[pin_and2_b]) wire_q_2.connect_pin(inst_and2_2.pins[pin_and2_q]) wire_q_1.connect_pin(inst_or2.pins[pin_or2_a]) wire_q_2.connect_pin(inst_or2.pins[pin_or2_b]) wire_o.connect_pin(pin_widget_o) wire_o.connect_pin(inst_or2.pins[pin_or2_q]) sdn.compose(netlist, 'test.edf')