def check_cache(cls, ram_address, control):
instruction = next(
(instruct for instruct in cls.cache if ram_address in cls.cache),
None)
if instruction:
return instruction
else:
from src.bus import Bus
instruction = Bus.fetch_from_ram(ram_address, control)
if len(cls.cache) >= 10:
cls.lfu()
cls.cache.append({
ram_address: instruction,
'timestamp': time.time()
})
return instruction
def ask_for_ram(address, control):
from src.bus import Bus
print('cpu address: ', address)
addr = Bus.fetch_from_ram(address, control)
CPU.process_instruction(addr['instruction'])
time.sleep(0.1)