Beispiel #1
0
def Zero(nbit):
    global CELLS
    from st_model import CELLS

    cell = CELLS[-1]

    if not (cell._st_vdds) or not (cell._st_vsss):
        raise "\n[Stratus ERROR] : there is no alim.\n"

    num_net = len(cell._TAB_NETS_OUT)
    cell._TAB_NETS_OUT += [Signal("zero_s%d" % num_net, nbit)]

    #   "1 bit constant" => directly instanciate the virtual cell "Zero" cell
    # "> 1 bit constant" => generate a model
    #  if nbit == 1:
    #    inst_name = "zero"
    #  else:
    inst_name = "zero_%d" % nbit
    Generate("Zero", inst_name, param={'nbit': nbit})
    Inst(inst_name,
         map={
             'nq': cell._TAB_NETS_OUT[num_net],
             'vdd': cell._st_vdds[0],
             'vss': cell._st_vsss[0]
         })

    return cell._TAB_NETS_OUT[num_net]
Beispiel #2
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  def Extend ( self, width, type ) :
    global CELLS

    from st_model import CELLS
    from st_const import Zero, One
        
    cell = CELLS[-1]

    if self._arity >= width :
      err = "\n[Stratus ERROR] Extend : the net " + self._name + \
            " can not be extended to " + str(width) + " bits, it's arity is already " + str(self._arity) + ".\n"
      raise Exception ( err )
    
    num_net             = len ( cell._TAB_NETS_OUT )
    cell._TAB_NETS_OUT += [Signal ( "%s_ext_%d_%d" % ( self._name, width, num_net ), width )]

    name = "extend_%d_%d_%s" % ( self._arity, width, type )

    Generate ( "Extend", name, param = { 'nbit0' : self._arity, 'nbit1' : width, 'type' : type } )

    Inst ( name
         , map = { 'i'   : self
                 , 'o'   : cell._TAB_NETS_OUT[num_net]
                 , 'vdd' : cell._st_vdds[0]
                 , 'vss' : cell._st_vsss[0]
                 }
         )

    return cell._TAB_NETS_OUT[num_net]
Beispiel #3
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    def __invert__(self):
        global CELLS
        from st_model import CELLS

        cell = CELLS[-1]

        if not (cell._st_vdds) or not (cell._st_vsss):
            err = "\n[Stratus ERROR] : there is no alim.\n"
            raise Exception(err)

        # Creation of the output net with the right size
        num_net = len(cell._TAB_NETS_OUT)
        cell._TAB_NETS_OUT += [Signal("inv_o%d" % num_net, self._arity)]

        invMap = {
            'nq': cell._TAB_NETS_OUT[num_net],
            'vdd': cell._st_vdds[0],
            'vss': cell._st_vsss[0]
        }
        if self._st_cell._not == 'DpgenInv': invMap['i0'] = self
        else: invMap['i'] = self

        #    if ( self._st_cell._not == "Inv" ) and ( self._arity == 1 ) :
        #      inst_name = self._st_cell._not.lower()
        #    else :
        inst_name = self._st_cell._not.lower()
        inst_name = re.sub("\.", "_", inst_name)
        inst_name += "_"
        inst_name += str(self._arity)

        Generate(self._st_cell._not, inst_name, param={'nbit': self._arity})

        Inst(inst_name, map=invMap)

        return cell._TAB_NETS_OUT[num_net]
Beispiel #4
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  def comparaison ( self, nb, egal ) :
    global CELLS
    from st_model import CELLS
        
    cell = CELLS[-1]
    
    if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise Exception ( "\n[Stratus ERROR] : threre is no alim.\n" )

    # Initialisation of the output net
    num_net             = len ( cell._TAB_NETS_OUT )
    cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, 1 )]
  
    inst_name = self._st_cell._comp.lower()
    inst_name = re.sub ( "\.", "_", inst_name )
    inst_name += "_"
    inst_name += str(self._arity)
    inst_name += "_"
    inst_name += str(nb)
    if egal : inst_name += "eq"

    Generate ( self._st_cell._comp, inst_name, param = { 'nbit' : self._arity, 'nb' : nb, 'egal' : egal } )
    Inst ( inst_name
         , map = { "netin"  : self
                 , "netout" : cell._TAB_NETS_OUT[num_net]
                 , 'vdd'    : cell._st_vdds[0]
                 , 'vss'    : cell._st_vsss[0]
                 }
         )

    return cell._TAB_NETS_OUT[num_net]
Beispiel #5
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  def muxList ( self, nets ) :
    global CELLS
    from st_model import CELLS
    
    cell = CELLS[-1]
    
    if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise Exception ( "\n[Stratus ERROR] : there is no alim.\n" )
    
    long = 0
    for i in range ( len ( nets ) ) :
      if nets[i] : long = nets[i]._arity

    # Error : if no input net
    if not ( long ) : raise Exception ( "\n[Stratus ERROR] Mux : there are no input nets.\n" )
    
    # Instanciation of a zero cell if needed 
    for net in nets :
      if net == 0 :
        from st_const import Zero
        num_net             = len ( cell._TAB_NETS_OUT )
        cell._TAB_NETS_OUT += [Signal ( "sig0_%d" % num_net, long )]
        cell._TAB_NETS_OUT[num_net] <= Zero ( long )
        break

    # Creation of the map
    map_mux = { 'cmd' : self
              , 'vdd' : cell._st_vdds[0]
              , 'vss' : cell._st_vsss[0]
              }
        
    i = 0
    for net in nets :
      if net : map_mux['i%d' % i] = net
      else   : map_mux['i%d' % i] = cell._TAB_NETS_OUT[num_net]
    
      i += 1

    # Initialisation of the output net
    num_net             = len ( cell._TAB_NETS_OUT )
    cell._TAB_NETS_OUT += [Signal ( "net_out_%d" % num_net, long )]
    
    map_mux ['q']  = cell._TAB_NETS_OUT[num_net]
    
    inst_name = self._st_cell._mux.lower()
    inst_name = re.sub ( "\.", "_", inst_name )
    inst_name += "_"
    inst_name += str(long)
    inst_name += "_"
    inst_name += str(self._arity)

    Generate ( self._st_cell._mux, inst_name, param = { 'nbit' : long, 'nbit_cmd' : self._arity } )
    Inst     ( inst_name, map = map_mux )

    return cell._TAB_NETS_OUT[num_net]
Beispiel #6
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    def Reg(self, inputNet):
        global CELLS
        from st_model import CELLS

        cell = CELLS[-1]

        if not inputNet._arity:
            raise Exception(
                "\n[Stratus ERROR] Reg : The input net does not have a positive arity.\n"
            )
        if not self._arity:
            raise Exception(
                "\n[Stratus ERROR] Reg : The clock does not have a positive arity.\n"
            )
        if not (cell._st_vdds) or not (cell._st_vsss):
            raise Exception("\n[Stratus ERROR] there is no alim.\n")

        # Creation of the output net with the right size
        num_net = len(cell._TAB_NETS_OUT)
        cell._TAB_NETS_OUT += [Signal("reg_o%d" % num_net, inputNet._arity)]

        #    if ( self._st_cell._reg == "Sff1" ) and ( inputNet._arity == 1 ) :
        #      inst_name = "sff1"
        #    else :
        #      inst_name = self._st_cell._reg.lower()
        #      inst_name = re.sub ( "\.", "_", inst_name )
        #      inst_name += "_"
        #      inst_name += str(inputNet._arity)
        #
        #      Generate ( self._st_cell._reg, inst_name, param = { 'nbit' : inputNet._arity } )

        inst_name = self._st_cell._reg.lower()
        inst_name = re.sub("\.", "_", inst_name)
        inst_name += "_"
        inst_name += str(inputNet._arity)

        Generate(self._st_cell._reg,
                 inst_name,
                 param={'nbit': inputNet._arity})

        Inst(inst_name,
             map={
                 'i': inputNet,
                 'ck': self,
                 'q': cell._TAB_NETS_OUT[num_net],
                 'vdd': cell._st_vdds[0],
                 'vss': cell._st_vsss[0]
             })

        return cell._TAB_NETS_OUT[num_net]
Beispiel #7
0
  def Shift ( self, inputNet, direction, type ) :
    global CELLS
    from st_model import CELLS

    cell = CELLS[-1]

    if not inputNet._arity : raise Exception ( "\n[Stratus ERROR] Shift : The input net does not have a positive arity.\n" )
    if not self._arity     : raise Exception ( "\n[Stratus ERROR] Shift : The command net does not have a positive arity.\n" )
    if not ( cell._st_vdds ) or not ( cell._st_vsss ) : raise Exception ( "\n[Stratus ERROR] there is no alim.\n" )
    # Wrong parameters :
    if direction not in ( "left", "right" ) : raise Exception ( "\n[Stratus ERROR] Shift : The direction parameter must be \"left\" or \"right\".\n" )
    if type not in ( "logical", "arith", "circular" ) : raise Exception ( "\n[Stratus ERROR] Shift : The type parameter must be \"logical\" or \"arith\" or \"circular\".\n" )

    # Creation of the output net with the right size
    num_net             =  len ( cell._TAB_NETS_OUT )
    cell._TAB_NETS_OUT += [Signal ( "sh_o%d" % num_net, inputNet._arity )]

    # Initialisation of shiftType
    if direction is "left" :
      if   type is "logical" : shiftType = 0x12
      elif type is "arith"   : shiftType = 0xa
      else                   : shiftType = 0x6
    else :
      if   type is "logical" : shiftType = 0x11
      elif type is "arith"   : shiftType = 0x9
      else                   : shiftType = 0x5

    inst_name = self._st_cell._shift.lower()
    inst_name = re.sub ( "\.", "_", inst_name )
    inst_name += "_"
    inst_name += type
    inst_name += "_"
    inst_name += str(inputNet._arity)

    Generate ( self._st_cell._shift, inst_name, param = { 'nbit' : inputNet._arity, 'type' : shiftType } )
    Inst ( inst_name
         , map = { 'cmd' : self
                 , 'i'   : inputNet
                 , 's'   : cell._TAB_NETS_OUT[num_net]
                 , 'vdd' : cell._st_vdds[0]
                 , 'vss' : cell._st_vsss[0]
                 }
         )

    return cell._TAB_NETS_OUT[num_net]
Beispiel #8
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    def bool(self, other_net, model):
        global CELLS
        from st_model import CELLS

        cell = CELLS[-1]

        if model == self._st_cell._and: f = "&"
        elif model == self._st_cell._or: f = "|"
        elif model == self._st_cell._xor: f = "^"
        if self._arity - other_net._arity:
            err = "\n[Stratus ERROR] " + f + " : the nets " + self._name + " and " + other_net._name + " must have the same lenght.\n"
            raise Exception(err)

        # Creation of the output net with the right size
        num_net = len(cell._TAB_NETS_OUT)
        cell._TAB_NETS_OUT += [Signal("bool_o%d" % num_net, self._arity)]

        if not (cell._st_vdds) or not (cell._st_vsss):
            err = "\n[Stratus ERROR] : there is no alim.\n"
            raise Exception(err)

#    if ( model in ( "A2", "O2", "Xr2" ) ) and ( self._arity == 1 ) and ( other_net._arity == 1 ) :
#      inst_name = model.lower()
#
#    else :
        inst_name = model.lower()
        inst_name = re.sub("\.", "_", inst_name)
        inst_name += "_"
        inst_name += str(self._arity)

        Generate(model, inst_name, param={'nbit': self._arity})

        Inst(inst_name,
             map={
                 'i0': self,
                 'i1': other_net,
                 'q': cell._TAB_NETS_OUT[num_net],
                 'vdd': cell._st_vdds[0],
                 'vss': cell._st_vsss[0]
             })

        return cell._TAB_NETS_OUT[num_net]
Beispiel #9
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    def arithgen(self, other_net, function, parameter={}):
        global CELLS
        from st_model import CELLS

        cell = CELLS[-1]

        if not function:
            err = "\n[Stratus ERROR] / : to be done.\n"
            raise Exception(err)

        if not (cell._st_vdds) or not (cell._st_vsss):
            err = "\n[Stratus ERROR] there is no alim in cell %s.\n" % str(
                cell._name)
            raise Exception(err)

        # Creation of the output net with the right size
        num_net = len(cell._TAB_NETS_OUT)

        if function == self._st_cell._add:
            if self._st_cell._extended:
                cell._TAB_NETS_OUT += [
                    Signal("add_o%d" % num_net,
                           max(self._arity, other_net._arity) + 1)
                ]
            else:
                cell._TAB_NETS_OUT += [
                    Signal("add_o%d" % num_net,
                           max(self._arity, other_net._arity))
                ]
        elif function == self._st_cell._sub:
            if self._st_cell._extended:
                cell._TAB_NETS_OUT += [
                    Signal("sub_o%d" % num_net,
                           max(self._arity, other_net._arity) + 1)
                ]
            else:
                cell._TAB_NETS_OUT += [
                    Signal("sub_o%d" % num_net,
                           max(self._arity, other_net._arity))
                ]
        elif function == self._st_cell._mult:
            cell._TAB_NETS_OUT += [
                Signal("mul_o%d" % num_net, self._arity + other_net._arity)
            ]

        arithParam = parameter
        if not self._st_cell._signed and function == self._st_cell._mult:
            name1 = re.sub(r"\[([0-9]+):([0-9]+)\]", r"\1\2",
                           self._name) + "ext"
            name2 = re.sub(r"\[([0-9]+):([0-9]+)\]", r"\1\2",
                           other_net._name) + "ext"
            i0ext = Signal(name1, self._arity + 1)
            i1ext = Signal(name2, other_net._arity + 1)
            i0ext <= self.Extend(self._arity + 1, 'zero')
            i1ext <= other_net.Extend(other_net._arity + 1, 'zero')

            arithParam['nbit0'] = self._arity + 1
            arithParam['nbit1'] = other_net._arity + 1

            arithMap = {
                'i0': i0ext,
                'i1': i1ext,
                'o': cell._TAB_NETS_OUT[num_net],
                'vdd': cell._st_vdds[0],
                'vss': cell._st_vsss[0]
            }

        else:

            arithParam['nbit0'] = self._arity
            arithParam['nbit1'] = other_net._arity

            arithMap = {
                'i0': self,
                'i1': other_net,
                'o': cell._TAB_NETS_OUT[num_net],
                'vdd': cell._st_vdds[0],
                'vss': cell._st_vsss[0]
            }

        inst_name = function.lower()
        inst_name = re.sub("\.", "_", inst_name)
        for p in arithParam:
            inst_name += "_%s_%s" % (str(p).lower(), str(
                arithParam[p]).lower())

        Generate(function, inst_name, param=arithParam)
        Inst(inst_name, map=arithMap)

        return cell._TAB_NETS_OUT[num_net]
Beispiel #10
0
    def __le__(self, net):
        global CELLS
        from st_model import CELLS

        cell = CELLS[-1]

        ### Initialisation of net representing a constant ###
        if type(net) == bytes:
            from st_const import Constant

            if not (cell._st_vdds) or not (cell._st_vsss):
                err = "\n[Stratus ERROR] : there is no alim.\n"
                raise Exception(err)

            constParam = {'nb': net}
            string = Constant.getString(constParam)

            num_net = len(cell._TAB_NETS_OUT)
            cell._TAB_NETS_OUT += [Signal("cst_o%d" % num_net, len(string))]

            # 3 possible constant operator output name (nq,q,output) => 3 differents map
            if string == "0":
                inst_name = "zero"
                map_cst = {
                    'nq': cell._TAB_NETS_OUT[num_net],
                    'vdd': cell._st_vdds[0],
                    'vss': cell._st_vsss[0]
                }
            elif string == "1":
                inst_name = "one"
                map_cst = {
                    'q': cell._TAB_NETS_OUT[num_net],
                    'vdd': cell._st_vdds[0],
                    'vss': cell._st_vsss[0]
                }
            else:
                inst_name = Constant.getModelName(constParam)
                map_cst = {
                    'o': cell._TAB_NETS_OUT[num_net],
                    'vdd': cell._st_vdds[0],
                    'vss': cell._st_vsss[0]
                }
                Generate("Constant", inst_name, param=constParam)

            Inst(inst_name, map=map_cst)

            net = cell._TAB_NETS_OUT[num_net]

        ### Merging of two nets ###
        # Resizement of the output net if needed thanks to the input net's lenght
        if not (self._arity): self.create_net(self._name, net._arity)

        # Error if the nets don t have the same size
        if self._arity - net._arity:
            err = "\n[Stratus ERROR] <= : the nets " + self._name + " " + str(self._arity) + " and " + net._name + " " + str(net._arity) \
                + " must have the same lenght\n"
            raise Exception(err)

        # If the nets are virtual, Let s work with the corresponding real nets
        if self._real_net: netInCell = self._real_net
        else: netInCell = self

        if net._real_net: netToMerge = net._real_net
        else: netToMerge = net

        # Error if self is an input net
        if (netInCell._ext) and (netInCell._direct == "IN"):
            err = "\n[Stratus ERROR] <= : " + self._name + " One can not give a value to an input net.\n"
            raise Exception(err)

        if netToMerge._ext:
            err = "\n[Stratus ERROR] <= : " + self._name
            # Error if net is an output net
            if netToMerge._direct == "OUT":
                err += " One can not initialise a net with an output net.\n"
                # Error if net is an input net
            elif netToMerge._direct == "IN":
                err += " One can not initialise a net with an input net. The method Buffer() should be used.\n"
            raise Exception(err)

        # Construction of the tab if needed
        if not (len(netToMerge._to_merge)):
            for i in range(netToMerge._arity):
                netToMerge._to_merge.append(0)

        # Initialisation of _to_merge
        for i in range(net._arity):
            netToMerge._to_merge[i + net._ind] = [netInCell, i + self._ind]

        # Puts the net in the list of nets to merge in order to have them in the right order
        self._st_cell._st_merge.append(net)

        if self._st_cell._hur_cell:
            net.hur_merge()
            for i in range(net._arity):
                CRL.createPartRing(
                    self._st_cell._hur_cell,
                    netInCell._hur_net[i + self._ind].getName()
                )  # FIXME plante avec le adder mixed dans un cas particulier indetermine ....