def __init__(self, name='Fpga', description='Fpga Container', **kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(axi.AxiVersion(offset=0x00000000, ))
self.add(ssi.SsiPrbsTx(offset=0x00040000, ))
self.add(ssi.SsiPrbsRx(offset=0x00050000, ))
self.add(rssi.RssiCore(offset=0x00070000, ))
self.add(udp.UdpEngine(
offset=0x00078000,
numSrv=2,
expand=False,
))
self.add(
ethPhy.TenGigEthReg(
offset=0x80000000,
writeEn=True,
expand=True,
))
def __init__(self, **kwargs):
super().__init__(**kwargs)
self.add(axi.AxiVersion(offset=0x0000, ))
self.add(ssi.SsiPrbsTx(offset=0x1000, ))
self.add(ssi.SsiPrbsRx(offset=0x2000, ))
def __init__(self, name='Fpga', description='Fpga Container', **kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(rssi.RssiCore(offset=0xA4010000,
# expand = False,
))
self.add(ssi.SsiPrbsTx(offset=0xA4020000,
# expand = False,
))
self.add(ssi.SsiPrbsRx(offset=0xA4030000,
# expand = False,
))
def __init__(self,
name="pciServer",
description="DMA Loopback Testing",
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# Create PCIE memory mapped interface
self.memMap = rogue.hardware.axi.AxiMemMap(args.dev)
self.perf = args.perf
if (self.perf is False):
self.dmaStream = [[None for x in range(args.numVc)]
for y in range(args.numLane)]
self.prbsRx = [[None for x in range(args.numVc)]
for y in range(args.numLane)]
self.prbsTx = [[None for x in range(args.numVc)]
for y in range(args.numLane)]
# Add the PCIe core device to base
self.add(
pcie.AxiPcieCore(
offset=0x00000000,
memBase=self.memMap,
numDmaLanes=args.numLane,
expand=False,
))
if (self.perf is True):
self.add(
ssi.SsiPrbsTx(
offset=(0x0040_0000 + 1 * 0x1_0000),
memBase=self.memMap,
expand=True,
))
self.add(
def __init__(self,
name='Fpga',
fpgaType='',
commType='',
description='Fpga Container',
**kwargs):
super().__init__(name=name, description=description, **kwargs)
#############
# Add devices
#############
self.add(axi.AxiVersion(
offset=0x00000000,
expand=False,
))
if (fpgaType == '7series'):
self.add(xil.Xadc(
offset=0x00010000,
expand=False,
))
if (fpgaType == 'ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset=0x00020000,
expand=False,
))
self.add(
MbSharedMem(
name='MbSharedMem',
offset=0x00030000,
size=0x10000,
expand=False,
))
self.add(ssi.SsiPrbsTx(
offset=0x00040000,
expand=False,
))
self.add(ssi.SsiPrbsRx(
offset=0x00050000,
expand=False,
))
if (commType == 'eth'):
self.add(rssi.RssiCore(
offset=0x00070000,
expand=False,
))
self.add(
axi.AxiStreamMonitoring(
name='AxisMon',
offset=0x00080000,
numberLanes=2,
expand=False,
))
self.add(
MbSharedMem(
name='TestEmptyMem',
offset=0x80000000,
size=0x80000000,
expand=False,
))
def __init__(self,
name="pciServer",
description="DMA Loopback Testing",
**kwargs):
super().__init__(name=name, description=description, **kwargs)
# Create an arrays to be filled
self.dmaStream = [[None for x in range(args.numVc)]
for y in range(args.numLane)]
self.prbsRx = [[None for x in range(args.numVc)]
for y in range(args.numLane)]
self.prbTx = [[None for x in range(args.numVc)]
for y in range(args.numLane)]
# Create PCIE memory mapped interface
self.memMap = rogue.hardware.axi.AxiMemMap(args.dev, )
# Add the PCIe core device to base
self.add(
pcie.AxiPcieCore(
offset=0x00000000,
memBase=self.memMap,
numDmaLanes=args.numLane,
expand=True,
))
for i in range(4):
self.add(
axi.AxiMemTester(
name=f'AxiMemTester[{i}]',
offset=0x0010_0000 + i * 0x1_0000,
memBase=self.memMap,
expand=True,
))
# Loop through the DMA channels
for lane in range(args.numLane):
# Loop through the virtual channels
for vc in range(args.numVc):
if (args.fwTx):
# Add the FW PRBS TX Module
self.add(
ssi.SsiPrbsTx(
name=('FwPrbsTx[%d][%d]' % (lane, vc)),
memBase=self.memMap,
offset=0x00800000 + (0x10000 * lane) +
(0x1000 * (2 * vc + 0)),
expand=False,
))
if (args.fwRx):
# Add the FW PRBS RX Module
self.add(
ssi.SsiPrbsRx(
name=('FwPrbsRx[%d][%d]' % (lane, vc)),
memBase=self.memMap,
offset=0x00800000 + (0x10000 * lane) +
(0x1000 * (2 * vc + 1)),
expand=False,
))
# Loop through the DMA channels
for lane in range(args.numLane):
# Loop through the virtual channels
for vc in range(args.numVc):
# Set the DMA loopback channel
self.dmaStream[lane][vc] = rogue.hardware.axi.AxiStreamDma(
args.dev, (0x100 * lane) + vc, 1)
# self.dmaStream[lane][vc].setDriverDebug(0)
if (args.loopback):
# Loopback the PRBS data
self.dmaStream[lane][vc] >> self.dmaStream[lane][vc]
else:
if (args.swRx):
# Connect the SW PRBS Receiver module
self.prbsRx[lane][vc] = pr.utilities.prbs.PrbsRx(
name=('SwPrbsRx[%d][%d]' % (lane, vc)),
width=args.prbsWidth,
checkPayload=False,
expand=True,
)
self.dmaStream[lane][vc] >> self.prbsRx[lane][vc]
self.add(self.prbsRx[lane][vc])
if (args.swTx):
# Connect the SW PRBS Transmitter module
self.prbTx[lane][vc] = pr.utilities.prbs.PrbsTx(
name=('SwPrbsTx[%d][%d]' % (lane, vc)),
width=args.prbsWidth,
expand=False,
)
self.prbTx[lane][vc] >> self.dmaStream[lane][vc]
self.add(self.prbTx[lane][vc])
@self.command()
def EnableAllFwTx():
fwTxDevices = root.find(typ=ssi.SsiPrbsTx)
for tx in fwTxDevices:
tx.TxEn.set(True)
@self.command()
def DisableAllFwTx():
fwTxDevices = root.find(typ=ssi.SsiPrbsTx)
for tx in fwTxDevices:
tx.TxEn.set(False)
def __init__( self,
name = 'Fpga',
fpgaType = '',
commType = '',
description = 'Fpga Container',
**kwargs):
super().__init__(name=name,description=description, **kwargs)
self.add(axi.AxiVersion(
offset = 0x00000000,
expand = True,
))
if(fpgaType=='7series'):
self.add(xil.Xadc(
offset = 0x00010000,
expand = False,
))
if(fpgaType=='ultrascale'):
self.add(xil.AxiSysMonUltraScale(
offset = 0x00020000,
expand = False,
))
# self.add(MbSharedMem(
# name = 'MbSharedMem',
# offset = 0x00030000,
# size = 0x10000,
# expand = False,
# ))
self.add(ssi.SsiPrbsTx(
offset = 0x00040000,
expand = False,
))
self.add(ssi.SsiPrbsRx(
offset = 0x00050000,
expand = False,
))
if ( commType == 'eth' ):
self.add(rssi.RssiCore(
offset = 0x00070000,
expand = False,
))
# self.add(udp.UdpEngine(
# offset = 0x00078000,
# numSrv = 1,
# expand = False,
# ))
self.add(axi.AxiStreamMonAxiL(
name = 'AxisMon',
offset = 0x00080000,
numberLanes = 2,
expand = False,
))
def __init__(self,
name="Top",
description="Container for EpixQuad",
memMap=None,
**kwargs):
super().__init__(name=name, description=description, **kwargs)
@self.command()
def ClearAsicMatrix():
# save TrigEn state and stop
self.SystemRegs.enable.set(True)
trigEn = self.SystemRegs.TrigEn.get()
self.SystemRegs.TrigEn.set(False)
# clear matrix in all enabled ASICs
for i in range(16):
self.Epix10kaSaci[i].ClearMatrix()
# restore TrigEn state
self.SystemRegs.TrigEn.set(trigEn)
######################################################################
# Add devices
self.add(
ePixQuad.EpixVersion(
name='AxiVersion',
memBase=memMap,
offset=0x00000000,
expand=False,
))
self.add(
ePixQuad.SystemRegs(
name='SystemRegs',
memBase=memMap,
offset=0x00100000,
expand=False,
))
self.add(
ePixQuad.AcqCore(
name='AcqCore',
memBase=memMap,
offset=0x01000000,
expand=False,
))
self.add(
ePixQuad.RdoutCore(
name='RdoutCore',
memBase=memMap,
offset=0x01100000,
expand=False,
))
self.add(
axi.AxiStreamMonitoring(
name='RdoutStreamMonitoring',
memBase=memMap,
offset=0x01300000,
expand=False,
))
self.add(
ssi.SsiPrbsTx(
name='PrbsTx',
memBase=memMap,
offset=0x01400000,
expand=False,
enabled=False,
))
self.add(
ePixQuad.PseudoScopeCore(
name='PseudoScopeCore',
memBase=memMap,
offset=0x01200000,
expand=False,
))
if (hwType != 'simulation'):
self.add(
ePixQuad.VguardDac(
name='VguardDac',
memBase=memMap,
offset=0x00500000,
expand=False,
))
self.add(
ePixQuad.EpixQuadMonitor(
name='EpixQuadMonitor',
memBase=memMap,
offset=0x00700000,
expand=False,
))
##################################################
## DO NOT MAP. MICROBLAZE IS THE ONLY
## AXI LITE MASTER THAT SHOULD ACCESS THIS DEVICE
##################################################
#self.add(ePixQuad.AxiI2cMaster(
# name = 'AxiI2cMaster',
# memBase = memMap,
# offset = 0x00600000,
# expand = False,
# hidden = True,
#))
self.add(
axi.AxiMemTester(
name='AxiMemTester',
memBase=memMap,
offset=0x00400000,
expand=False,
enabled=False,
))
for i in range(16):
asicSaciAddr = [
0x04000000, 0x04400000, 0x04800000, 0x04C00000, 0x05000000,
0x05400000, 0x05800000, 0x05C00000, 0x06000000, 0x06400000,
0x06800000, 0x06C00000, 0x07000000, 0x07400000, 0x07800000,
0x07C00000
]
self.add(
epix.Epix10kaAsic(
name=('Epix10kaSaci[%d]' % i),
memBase=memMap,
offset=asicSaciAddr[i],
enabled=False,
expand=False,
size=0x3fffff,
))
self.add(
ePixQuad.SaciConfigCore(
name='SaciConfigCore',
memBase=memMap,
offset=0x08000000,
expand=False,
enabled=False,
simSpeedup=(hwType == 'simulation'),
))
if (hwType != 'simulation'):
confAddr = [
0x02A00000, 0x02A00800, 0x02A01000, 0x02A01800, 0x02B00000,
0x02B00800, 0x02B01000, 0x02B01800, 0x02C00000, 0x02C00800
]
for i in range(10):
self.add(
analog_devices.Ad9249ConfigGroup(
name=('Ad9249Config[%d]' % i),
memBase=memMap,
offset=confAddr[i],
enabled=False,
expand=False,
))
for i in range(10):
self.add(
analog_devices.Ad9249ReadoutGroup(
name=('Ad9249Readout[%d]' % i),
memBase=memMap,
offset=(0x02000000 + i * 0x00100000),
enabled=False,
expand=False,
fpga='ultrascale',
))
self.add(
ePixQuad.AdcTester(
name='Ad9249Tester',
memBase=memMap,
offset=0x02D00000,
enabled=False,
expand=False,
hidden=False,
))
if (hwType != 'simulation'):
self.add(
cypress.CypressS25Fl(
offset=0x00300000,
memBase=memMap,
expand=False,
addrMode=True,
hidden=True,
))
# ADC startup parameters
self.adcRstTime = 0.01
self.serRstTime = 0.01
self.retries = 5
if path.exists('ePixQuadAdcTrainingData.txt'):
with open('ePixQuadAdcTrainingData.txt') as f:
self.allDelays = f.readlines()
self.allDelays = [int(i) for i in self.allDelays]
if len(self.allDelays) < 90:
self.allDelays = [-1] * 90
else:
self.allDelays = [-1] * 90
@self.command()
def AdcStartup():
self.SystemRegs.enable.set(True)
self.Ad9249Tester.enable.set(True)
self.RdoutCore.enable.set(True)
self.AcqCore.enable.set(True)
self.PseudoScopeCore.enable.set(True)
for adc in range(10):
self.Ad9249Readout[adc].enable.set(True)
self.Ad9249Config[adc].enable.set(True)
# disable and stop all internal ADC startup activity
self.SystemRegs.AdcBypass.set(True)
# Wait 100 ms
time.sleep(0.1)
#load trained delays
for adc in range(10):
newDly = self.allDelays[adc * 9]
if newDly >= 0:
self.Ad9249Readout[adc].FrameDelay.set(0x200 + newDly)
else:
print("Bad stored delay. Train ADCs!")
for lane in range(8):
newDly = self.allDelays[adc * 9 + lane + 1]
if newDly >= 0:
self.Ad9249Readout[adc].ChannelDelay[lane].set(0x200 +
newDly)
else:
print("Bad stored delay. Train ADCs!")
# test ADCs and reset if needed
for adc in range(10):
while True:
if self.testAdc(self, adc, 0) < 0 or self.testAdc(
self, adc, 1) < 0:
self.resetAdc(self, adc)
else:
break
# re-enable internal ADC startup
self.SystemRegs.AdcBypass.set(False)
self.Ad9249Tester.enable.set(False)
print('Done')
@self.command()
def AdcTrain():
self.SystemRegs.enable.set(True)
self.Ad9249Tester.enable.set(True)
for adc in range(10):
self.Ad9249Readout[adc].enable.set(True)
self.Ad9249Config[adc].enable.set(True)
# disable and stop all internal ADC startup activity
self.SystemRegs.AdcBypass.set(True)
# Wait 100 ms
time.sleep(0.1)
for adc in range(10):
result = 0
while True:
self.resetAdc(self, adc)
prevDly = self.Ad9249Readout[adc].FrameDelay.get()
newDly = self.trainFrameAdc(self, adc, self.retries)
# skip ADC if the frame training failed all times
if newDly >= 0:
result = result + 1
print('Diff delay %d' % (prevDly - newDly))
self.Ad9249Readout[adc].FrameDelay.set(0x200 + newDly)
self.allDelays[adc * 9] = newDly
# otherwise train data lanes
for lane in range(8):
prevDly = self.Ad9249Readout[adc].ChannelDelay[
lane].get()
newDly = self.trainDataLaneAdc(
self, adc, lane, self.retries)
if newDly >= 0:
result = result + 1
print('Diff delay %d' % (prevDly - newDly))
self.Ad9249Readout[adc].ChannelDelay[lane].set(
0x200 + newDly)
self.allDelays[adc * 9 + lane + 1] = newDly
if result < 9:
print('ADC %d failed. Retrying forever.' % (adc))
result = 0
else:
break
self.Ad9249Tester.enable.set(False)
# flash training data
self.flashAdcDelays(self)
# save training data
with open('ePixQuadAdcTrainingData.txt', 'w') as f:
for item in self.allDelays:
f.write("%s\n" % item)
# re-enable internal ADC startup
self.SystemRegs.AdcBypass.set(False)
@self.command()
def ClearAdcProm():
self.CypressS25Fl.enable.set(True)
self.CypressS25Fl.resetFlash()
# erase 64kB per sector ERASE_SIZE = 0x10000
# use space at 48MB (mcs size 16MB)
# mcs end 0xf43efc
self.CypressS25Fl.eraseCmd(0x3000000)
# create empty prom data array
writeArray = [0] * 64
self.CypressS25Fl.setDataReg(writeArray)
self.CypressS25Fl.writeCmd(0x3000000)
# Wait for last transaction to finish
self.CypressS25Fl.waitForFlashReady()
# Start address of a burst transfer
self.CypressS25Fl.readCmd(0x3000000)
# Get the data
readArray = self.CypressS25Fl.getDataReg()
if readArray != writeArray:
click.secho(
"\n\n\
***************************************************\n\
***************************************************\n\
Writing ADC constants to PROM failed !!!!!! \n\
***************************************************\n\
***************************************************\n\n",
bg='red',
)
else:
click.secho(
"\n\n\
***************************************************\n\
***************************************************\n\
Writing ADC constants to PROM done \n\
***************************************************\n\
***************************************************\n\n",
bg='green',
)