def generate_top_ral(top: Dict[str, object], name_to_block: Dict[str, IpBlock],
dv_base_prefix: str, out_path: str):
# construct top ral block
regwidth = int(top['datawidth'])
assert regwidth % 8 == 0
addrsep = regwidth // 8
# Generate a map from instance name to the block that it instantiates,
# together with a map of interface addresses.
inst_to_block = {} # type: Dict[str, str]
if_addrs = {} # type: Dict[Tuple[str, Optional[str]], int],
attrs = {} # type: Dict[str, str]
for module in top['module']:
inst_name = module['name']
block_name = module['type']
block = name_to_block[block_name]
if "attr" in module:
if module["attr"] not in [
'templated', 'reggen_top', 'reggen_only'
]:
raise ValueError(
'Unsupported value for attr field of {}: {!r}'.format(
inst_name, module["attr"]))
attrs[inst_name] = module["attr"]
inst_to_block[inst_name] = block_name
for if_name in block.reg_blocks.keys():
if_addr = int(module["base_addrs"][if_name], 0)
if_addrs[(inst_name, if_name)] = if_addr
# Collect up the memories to add
mems = []
for item in list(top.get("memory", [])):
byte_write = ('byte_write' in item
and item["byte_write"].lower() == "true")
data_intg_passthru = ('data_intg_passthru' in item
and item["data_intg_passthru"].lower() == "true")
size_in_bytes = int(item['size'], 0)
num_regs = size_in_bytes // addrsep
swaccess = access.SWAccess('top-level memory',
item.get('swaccess', 'rw'))
mems.append(
window.Window(name=item['name'],
desc='(generated from top-level)',
unusual=False,
byte_write=byte_write,
data_intg_passthru=data_intg_passthru,
validbits=regwidth,
items=num_regs,
size_in_bytes=size_in_bytes,
offset=int(item["base_addr"], 0),
swaccess=swaccess))
chip = Top(regwidth, name_to_block, inst_to_block, if_addrs, mems, attrs)
# generate the top ral model with template
return gen_dv(chip, dv_base_prefix, str(out_path))
def generate_top_ral(top: Dict[str, object], name_to_block: Dict[str, IpBlock],
dv_base_names: List[str], out_path: str):
# construct top ral block
regwidth = int(top['datawidth'])
assert regwidth % 8 == 0
addrsep = regwidth // 8
# Generate a map from instance name to the block that it instantiates,
# together with a map of interface addresses.
inst_to_block = {} # type: Dict[str, str]
if_addrs = {} # type: Dict[Tuple[str, Optional[str]], int],
attrs = {} # type: Dict[str, str]
for module in top['module']:
inst_name = module['name']
block_name = module['type']
block = name_to_block[block_name]
if "attr" in module:
if module["attr"] not in [
'templated', 'ipgen', 'reggen_top', 'reggen_only'
]:
raise ValueError(
'Unsupported value for attr field of {}: {!r}'.format(
inst_name, module["attr"]))
attrs[inst_name] = module["attr"]
inst_to_block[inst_name] = block_name
for if_name in block.reg_blocks.keys():
if_addr = int(module["base_addrs"][if_name], 0)
if_addrs[(inst_name, if_name)] = if_addr
# Collect up the memories to add
mems = []
for item in list(top.get("memory", [])):
mems.append(create_mem(item, addrsep, regwidth))
# Top-level may override the mem setting. Store the new type to name_to_block
# If no other instance uses the orignal type, delete it
original_types = set()
for module in top['module']:
if 'memory' in module.keys() and len(module['memory']) > 0:
newtype = '{}_{}'.format(module['type'], module['name'])
assert newtype not in name_to_block
block = deepcopy(name_to_block[module['type']])
name_to_block[newtype] = block
inst_to_block[module['name']] = newtype
original_types.add(module['type'])
for mem_name, item in module['memory'].items():
assert block.reg_blocks[mem_name]
assert len(block.reg_blocks[mem_name].windows) <= 1
item['name'] = mem_name
win = create_mem(item, addrsep, regwidth)
if len(block.reg_blocks[mem_name].windows) > 0:
blk_win = block.reg_blocks[mem_name].windows[0]
# Top can only add new info for mem, shouldn't overwrite
# existing configuration
assert win.items == blk_win.items
assert win.byte_write == blk_win.byte_write
assert win.data_intg_passthru == blk_win.data_intg_passthru
block.reg_blocks[mem_name].windows[0] = win
else:
block.reg_blocks[mem_name].windows.append(win)
for t in original_types:
if t not in inst_to_block.values():
del name_to_block[t]
chip = Top(regwidth, name_to_block, inst_to_block, if_addrs, mems, attrs)
# generate the top ral model with template
return gen_dv(chip, dv_base_names, str(out_path))
