# A registry bank of 32 registers each one 32 bits wide:
# they are the normal registers and the banked one. In particular:
memorySize = 5 * 1024 * 1024
# TODO: general description of each register
#GPR = General Purpouse Registers
regBank = trap.RegisterBank('GPR', 32,
32) #GPR is the name, 32 registers of 32 bits
regBank.setDefaultValue(memorySize - 16, 1)
processor.addRegBank(regBank)
# We define each special register as a single isolated register
# PC = SPR[0x0000]
pc = trap.Register('PC', 32)
pc.setDefaultValue('ENTRY_POINT')
processor.addRegister(pc)
# MSR = SPR[0x0001]
msrBitMask = {
'BE': (31, 31),
'IE': (30, 30),
'C': (29, 29),
'BIP': (28, 28),
'FSL': (27, 27),
'ICE': (26, 26),
'DZ': (25, 25),
'DCE': (24, 24),
'EE': (23, 23),
'EIP': (22, 22),
elif multiplier_size == '32_32':
LEON2Isa.isa.addDefines('#define MULT_SIZE_32_32\n')
# There are 8 global register, and a variable number of
# of 16-registers set; this number depends on the number of
# register windows
# global registers
globalRegs = trap.RegisterBank('GLOBAL', 8, 32)
globalRegs.setConst(0, 0)
processor.addRegBank(globalRegs)
# Register sets
windowRegs = trap.RegisterBank('WINREGS', 16*numRegWindows, 32)
processor.addRegBank(windowRegs)
# Program status register
psrBitMask = {'IMPL': (28, 31), 'VER': (24, 27), 'ICC_n': (23, 23), 'ICC_z': (22, 22), 'ICC_v': (21, 21), 'ICC_c': (20, 20), 'EC': (13, 13), 'EF': (12, 12), 'PIL': (8, 11), 'S': (7, 7), 'PS': (6, 6), 'ET': (5, 5), 'CWP': (0, 4)}
psrReg = trap.Register('PSR', 32, psrBitMask)
psrReg.setDefaultValue(0xF2000080)
processor.addRegister(psrReg)
# Window Invalid Mask Register
wimBitMask = {}
for i in range(0, 32):
wimBitMask['WIM_' + str(i)] = (i, i)
wimReg = trap.Register('WIM', 32, wimBitMask)
wimReg.setDefaultValue(0)
processor.addRegister(wimReg)
# Trap Base Register
tbrBitMask = {'TBA' : (12, 31), 'TT' : (4, 11)}
tbrReg = trap.Register('TBR', 32, tbrBitMask)
tbrReg.setDefaultValue(0)
processor.addRegister(tbrReg)
# Multiply / Divide Register
'F': (6, 6),
'mode': (0, 3)
}
spsrBank = trap.RegisterBank('SPSR', 5, 32, spsrBitMask)
processor.addRegBank(spsrBank)
# Current processor status register
cpsrBitMask = {
'N': (31, 31),
'Z': (30, 30),
'C': (29, 29),
'V': (28, 28),
'I': (7, 7),
'F': (6, 6),
'mode': (0, 3)
}
cpsr = trap.Register('CPSR', 32, cpsrBitMask)
cpsr.setDefaultValue(0x000000D3)
processor.addRegister(cpsr)
# Fake register (not presented in the architecture) indicating
# the processor ID: it is necessary in a multi-processor
# system
mp_id = trap.Register('MP_ID', 32)
mp_id.setDefaultValue('MPROC_ID')
processor.addRegister(mp_id)
# Now I set the alias: they can (and will) be used by the instructions
# to access the registers more easily. Note that, in general, it is
# responsibility of the programmer keeping the alias updated
regs = trap.AliasRegBank('REGS', 16, 'RB[0-15]')
regs.setOffset(15, 4)
processor.addAliasRegBank(regs)
FP = trap.AliasRegister('FP', 'REGS[11]')