fastFetch=True) processor.setBigEndian() #big endian processor.setWordsize(4, 8) #4 bytes per word, 8 bits per byte processor.setISA(MICROBLAZEIsa.isa) #lets set the instruction set # Ok, now we move to the description of more complicated processor # resources # A registry bank of 32 registers each one 32 bits wide: # they are the normal registers and the banked one. In particular: memorySize = 5 * 1024 * 1024 # TODO: general description of each register #GPR = General Purpouse Registers regBank = trap.RegisterBank('GPR', 32, 32) #GPR is the name, 32 registers of 32 bits regBank.setDefaultValue(memorySize - 16, 1) processor.addRegBank(regBank) # We define each special register as a single isolated register # PC = SPR[0x0000] pc = trap.Register('PC', 32) pc.setDefaultValue('ENTRY_POINT') processor.addRegister(pc) # MSR = SPR[0x0001] msrBitMask = { 'BE': (31, 31), 'IE': (30, 30), 'C': (29, 29), 'BIP': (28, 28),
elif multiplier_size == '16p': LEON2Isa.isa.addDefines('#define MULT_SIZE_16_PIPE\n') elif multiplier_size == '16': LEON2Isa.isa.addDefines('#define MULT_SIZE_16\n') elif multiplier_size == '32_8': LEON2Isa.isa.addDefines('#define MULT_SIZE_32_8\n') elif multiplier_size == '32_16': LEON2Isa.isa.addDefines('#define MULT_SIZE_32_16\n') elif multiplier_size == '32_32': LEON2Isa.isa.addDefines('#define MULT_SIZE_32_32\n') # There are 8 global register, and a variable number of # of 16-registers set; this number depends on the number of # register windows # global registers globalRegs = trap.RegisterBank('GLOBAL', 8, 32) globalRegs.setConst(0, 0) processor.addRegBank(globalRegs) # Register sets windowRegs = trap.RegisterBank('WINREGS', 16*numRegWindows, 32) processor.addRegBank(windowRegs) # Program status register psrBitMask = {'IMPL': (28, 31), 'VER': (24, 27), 'ICC_n': (23, 23), 'ICC_z': (22, 22), 'ICC_v': (21, 21), 'ICC_c': (20, 20), 'EC': (13, 13), 'EF': (12, 12), 'PIL': (8, 11), 'S': (7, 7), 'PS': (6, 6), 'ET': (5, 5), 'CWP': (0, 4)} psrReg = trap.Register('PSR', 32, psrBitMask) psrReg.setDefaultValue(0xF2000080) processor.addRegister(psrReg) # Window Invalid Mask Register wimBitMask = {} for i in range(0, 32): wimBitMask['WIM_' + str(i)] = (i, i) wimReg = trap.Register('WIM', 32, wimBitMask)
processor.systemc = True # Ok, now we move to the description of more complicated processor # resources # A registry bank of 22 registers each one 32 bits wide: # they are the normal registers and the banked one. In particular: # RB[0-7]: registers shared among all the modes # RB[8-12]: registers shared among all modes but FIQ # RB[13-14]: sp_user, lr_user # RB[15-16]: sp_svc, lr_svc # RB[17-18]: sp_abt, lr_abt # RB[19-20]: sp_und, lr_und # RB[21-22]: sp_irq, lr_irq # RB[23-29]: r8_fiq, r14_fiq regBank = trap.RegisterBank('RB', 30, 32) processor.addRegBank(regBank) # A registry bank of 5 registers each one 32 bits wide # they are the saved processor status registers for the different # execution modes; note that a bit mask for easily accessing # the different fields is provided # SPSR[0] = spsr_fiq, SPSR[1] = spsr_irq, SPSR[2] = spsr_svc, # SPSR[3] = spsr_abt, SPSR[4] = spsr_und spsrBitMask = { 'N': (31, 31), 'Z': (30, 30), 'C': (29, 29), 'V': (28, 28), 'I': (7, 7), 'F': (6, 6), 'mode': (0, 3)