class ms_flop(design.design):
"""
Memory address flip-flop
"""
pins = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"]
chars = utils.auto_measure_libcell(pins, "ms_flop", GDS["unit"], layer["boundary"])
def __init__(self, name):
design.design.__init__(self, name)
self.width = ms_flop.chars["width"]
self.height = ms_flop.chars["height"]
self.clk_offset = ms_flop.chars["clk"]
self.din_offset = ms_flop.chars["din"]
self.dout_offset = ms_flop.chars["dout"]
self.dout_bar_offset = ms_flop.chars["dout_bar"]
def delay(self, slew, load = 0.0):
#import pinv
# use inv to mimic the delay
# din -> mout
#ref = pinv.pinv("reference_inv")
#mid_load = ref.input_load()
#din_t_mout_delay = ref.delay(slew = slew, load = mid_load)
# mout -> out
#mout_t_out_delay = ref.delay(slew = slew, load = load)
#result = din_t_mout_delay + mout_t_out_delay
# dont k how to calculate this now, use constant in tech file
from tech import spice
result = self.return_delay(spice["msflop_delay"], spice["msflop_slew"])
return result
class bitcell(design.design):
"""
A single bit cell (6T, 8T, etc.) This module implements the
single memory cell used in the design. It is a hand-made cell, so
the layout and netlist should be available in the technology
library.
"""
pins = ["BL", "BR", "WL", "vdd", "gnd"]
chars = utils.auto_measure_libcell(pins, "cell_6t", GDS["unit"],
layer["boundary"])
def __init__(self, name="cell_6t"):
design.design.__init__(self, name)
debug.info(2, "Create bitcell object")
self.width = bitcell.chars["width"]
self.height = bitcell.chars["height"]
def delay(self, slew, load=0, swing=0.5):
# delay of bit cell is not like a driver(from WL)
# so the slew used should be 0
# it should not be slew dependent?
# because the value is there
# the delay is only over half transsmission gate
from tech import spice
r = spice["min_tx_r"] * 3
c_para = spice["min_tx_drain_c"]
result = self.cal_delay_with_rc(r=r,
c=c_para + load,
slew=slew,
swing=swing)
return result
class tri_gate(design.design):
"""
This module implements the tri gate cell used in the design for
bit-line isolation. It is a hand-made cell, so the layout and
netlist should be available in the technology library.
"""
pins = ["in", "en", "en_bar", "out", "gnd", "vdd"]
chars = utils.auto_measure_libcell(pins, "tri_gate", GDS["unit"], layer["boundary"])
def __init__(self, name):
design.design.__init__(self, name)
debug.info(2, "Create tri_gate object")
self.width = tri_gate.chars["width"]
self.height = tri_gate.chars["height"]
def delay(self, slew, load=0.0):
from tech import spice
r = spice["min_tx_r"]
c_para = spice["min_tx_drain_c"]
return self.cal_delay_with_rc(r = r, c = c_para+load, slew = slew)
def input_load(self):
return 9*spice["min_tx_gate_c"]
class sense_amp(design.design):
"""
This module implements the single sense amp cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library.
Sense amplifier to read a pair of bit-lines.
"""
pins = ["BL", "BR", "Dout", "SCLK", "vdd", "gnd"]
chars = utils.auto_measure_libcell(pins, "sense_amp", GDS["unit"],
layer["boundary"])
def __init__(self, name):
design.design.__init__(self, name)
debug.info(2, "Create Sense Amp object")
self.width = sense_amp.chars["width"]
self.height = sense_amp.chars["height"]
def delay(self, slew, load=0.0):
from tech import spice
r = spice["min_tx_r"] / (10)
c_para = spice["min_tx_drain_c"]
result = self.cal_delay_with_rc(r=r, c=c_para + load, slew=slew)
return self.return_delay(result.delay, result.slew)
class tri_gate(design.design):
"""
This module implements the tri gate cell used in the design for
bit-line isolation. It is a hand-made cell, so the layout and
netlist should be available in the technology library.
"""
pins = ["in", "en", "en_bar", "out", "gnd", "vdd"]
chars = utils.auto_measure_libcell(pins, "tri_gate", GDS["unit"],
layer["boundary"])
def __init__(self, name):
design.design.__init__(self, name)
debug.info(2, "Create tri_gate object")
self.width = tri_gate.chars["width"]
self.height = tri_gate.chars["height"]
class replica_bitcell(design.design):
"""
A single bit cell (6T, 8T, etc.)
This module implements the single memory cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library. """
pins = ["BL", "BR", "WL", "vdd", "gnd"]
chars = utils.auto_measure_libcell(pins, "replica_cell_6t", GDS["unit"],
layer["boundary"])
def __init__(self, name="replica_cell_6t"):
design.design.__init__(self, name)
debug.info(2, "Create bitcell object")
self.width = replica_bitcell.chars["width"]
self.height = replica_bitcell.chars["height"]
class sense_amp(design.design):
"""
This module implements the single sense amp cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library.
Sense amplifier to read a pair of bit-lines.
"""
pins = ["BL", "BR", "Dout", "SCLK", "vdd", "gnd"]
chars = utils.auto_measure_libcell(pins, "sense_amp", GDS["unit"],
layer["boundary"])
def __init__(self, name):
design.design.__init__(self, name)
debug.info(2, "Create Sense Amp object")
self.width = sense_amp.chars["width"]
self.height = sense_amp.chars["height"]
class write_driver(design.design):
"""
Tristate write driver to be active during write operations only.
This module implements the write driver cell used in the design. It
is a hand-made cell, so the layout and netlist should be available in
the technology library.
"""
pins = ["din", "BL", "BR", "en", "gnd", "vdd"]
chars = utils.auto_measure_libcell(pins, "write_driver", GDS["unit"],
layer["boundary"])
def __init__(self, name):
design.design.__init__(self, name)
debug.info(2, "Create write_driver object")
self.width = write_driver.chars["width"]
self.height = write_driver.chars["height"]
class ms_flop(design.design):
"""
Memory address flip-flop
"""
pins = ["din", "dout", "dout_bar", "clk", "vdd", "gnd"]
chars = utils.auto_measure_libcell(pins, "ms_flop", GDS["unit"],
layer["boundary"])
def __init__(self, name):
design.design.__init__(self, name)
self.width = ms_flop.chars["width"]
self.height = ms_flop.chars["height"]
self.clk_offset = ms_flop.chars["clk"]
self.din_offset = ms_flop.chars["din"]
self.dout_offset = ms_flop.chars["dout"]
self.dout_bar_offset = ms_flop.chars["dout_bar"]