def byte_sel(self):
"""Get selection bits array for this slave."""
def to_vector(name, start, length):
vector = ["%s(%d)" % (name, start-idx) for idx in range(length)]
return "(%s)" % " or ".join(vector)
(sel_width, _) = self.slave.wb_signal_width("SEL")
if sel_width == 0:
return None
sel_null = "'0'"
if sel_width > 1:
sel_null = "(others => '0')"
name = signal_name(self.slave, "sel_o")
sel_name = "master_sel%d" % (8*(2**(self.slave_byte_sel-1)))
if sel_width < self.slave_byte_sel:
step = self.slave_byte_sel//sel_width
sel = "&".join([to_vector(sel_name, idx-1, step)
for idx in range(self.slave_byte_sel, 0, -step)
])
else:
sel = sel_name
return ("%s <= %s when (%s = '1') else %s" % (name, sel, self.sel,
sel_null))
def mk_sel_bit(master, idx, sel_width, byte_width):
"""Creation byte selection bits for a specific master interface.
@param master: Master interface
@param idx: Byte selection bit index
@param sel_width: Master byte selection bus real width
@param byte_width: Master byte selection bus theoretical width.
"""
if sel_width == 0:
return None
elif sel_width == 1:
return signal_name(master, "sel_i")
elif sel_width == byte_width:
return mk_signal_bit(signal_name(master, "sel_i"), idx)
else:
idx2 = byte_width // sel_width
return mk_signal_bit(signal_name(master, "sel_i"), idx//idx2)
def control(self):
"""Get control signals for this slave."""
return [("%s <= %s when %s = '1' else '0'" %
(signal_name(self.slave, sig_type+"_o"),
("wbs_master_%s_i"%sig_type), self.sel))
for sig_type in ["cyc", "we", "stb"]
]
def ack(self):
"""Get acknowledge signals for this slave."""
name = "'1'"
if self.slave.has_signal("ACK"):
name = signal_name(self.slave, "ack_i")
return ("%s when (%s = '1')" % (name, self.sel))
def addr(self):
"""Get slave interface address bus.
"""
addr_width = self.slave.addr_width
addr_null = "'0'"
addr = "wbs_master_adr_i"
if addr_width > 1:
addr_null = "(others => '0')"
addr = "%s(%d downto %d)" % (addr, self.addr_low-1, self.sel_base)
else:
addr = "%s(%d)" % (addr, self.addr_low-1)
name = signal_name(self.slave, "adr_o")
return ("%s <= %s when (%s = '1') else %s" % (name, addr, self.sel,
addr_null))
def readdata(self, byte):
"""Generate slave data bus input signals.
"""
(m_dat_width, _) = self.master.wb_signal_width("DAT")
(_, s_dat_width) = self.slave.wb_signal_width("DAT")
if m_dat_width == 0 or s_dat_width == 0 or self.slave_byte_sel <= byte:
return None
s_name = signal_name(self.slave, "dat_i")
sel = "master_sel%d" % (8*(2**(self.slave_byte_sel-1)))
if self.slave_byte_sel == 1:
return [("%s when (%s='1' and %s='1')" % (s_name, self.sel, sel))]
return ["%s(%u downto %u) when (%s='1' and %s(%d)='1')" %
(s_name, idx*8+7, idx*8, self.sel, sel, idx)
for idx in range(byte, self.slave_byte_sel,
self.master_byte_sel)
]
def mk_sel_array(master, master_sel, slave_bytes):
"""Creation byte selection bits for a specific master interface.
@param master: Master interface
@param master_sel: Byte selection bit index
@param slave_bytes: Slave byte selection bus width
"""
if slave_bytes > len(master_sel):
bit_pow = slave_bytes / len(master_sel)
bit_cpt = 0
while 2**bit_cpt < bit_pow:
bit_cpt += 1
name = signal_name(master, "adr_i")
return (bit_cpt, [mk_sel_comb(name, master_sel, bit_cpt, idx)
for idx in range(slave_bytes)
])
else:
return (0, [master_sel[idx] for idx in range(slave_bytes)])
def writedata(self):
"""Generate slave data bus output signals.
"""
(_, m_dat_width) = self.master.wb_signal_width("DAT")
(s_dat_width, _) = self.slave.wb_signal_width("DAT")
if s_dat_width == 0:
return None
s_name = signal_name(self.slave, "dat_o")
m_name = "wbs_master_dat_i"
dat_nul = "(others => '0')"
if s_dat_width > m_dat_width:
m_name = "&".join([m_name] * (s_dat_width // m_dat_width))
elif s_dat_width < m_dat_width:
m_name = ("%s(%d downto 0)" % (m_name, s_dat_width-1))
return ("%s <= %s when (%s = '1') else %s" %
(s_name, m_name, self.sel, dat_nul))