def test_sformatf(self):
str1 = sv.sformatf("Number: %0d, String: %s", 555, "xxx")
self.assertRegex(str1, "Number: 555")
self.assertRegex(str1, "String: xxx")
test_str = [["Hexadecimal: %5h", 123], ["Time value: %0t", 55555]]
for pair in test_str:
str1 = sv.sformatf(pair[0], pair[1])
async def body(self):
status = 0
n = 0
# Initialize R with a random value then check against mirror
data = sv.urandom()
status = []
await self.model.R.write(status, data, parent=self)
self.check_status(status, "WRITE_FAIL")
status = []
await self.model.R.mirror(status, UVM_CHECK, parent=self)
self.check_status(status, "MIRROR FAIL")
# Perform a random number of INC operations
n = (sv.urandom() % 7) + 3
uvm_info("blk_R_test_seq", sv.sformatf("Incrementing R %0d times...",
n), UVM_NONE)
for i in range(n):
status = []
await self.model.CTL.write(status,
reg_fld_B_CTL_CTL.INC,
parent=self)
self.check_status(status, "WRITE " + str(i) + " FAIL")
data += 1
self.model.R.predict(data)
# Check the final value
status = []
await self.model.R.mirror(status, UVM_CHECK, parent=self)
self.check_status(status, "MIRROR2 FAIL")
# Perform a random number of DEC operations
n = (sv.urandom() % 8) + 2
uvm_info("blk_R_test_seq", sv.sformatf("Decrementing R %0d times...",
n), UVM_NONE)
for i in range(n):
status = []
await self.model.CTL.write(status,
reg_fld_B_CTL_CTL.DEC,
parent=self)
self.check_status(status, "WRITE B." + str(i) + " FAIL (DEC OP)")
data -= 1
self.model.R.predict(data)
# Check the final value
status = []
await self.model.R.mirror(status, UVM_CHECK, parent=self)
self.check_status(status, "MIRROR3 FAIL")
#
# Reset the register and check
status = []
await self.model.CTL.write(status, reg_fld_B_CTL_CTL.CLR, parent=self)
self.check_status(status, "WRITE4 FAIL")
self.model.R.predict(0)
status = []
await self.model.R.mirror(status, UVM_CHECK, parent=self)
self.check_status(status, "MIRROR4 FAIL")
def build(self):
# create
self.ID = reg_slave_ID.type_id.create("ID")
self.INDEX = reg_slave_INDEX.type_id.create("INDEX")
self.DATA = reg_slave_DATA.type_id.create("DATA")
for i in range(self.nsession):
rslave_sess = reg_slave_SESSION.type_id.create(
sv.sformatf("SESSION[%0d]", i))
self.SESSION.append(rslave_sess)
rslave_tables = reg_slave_TABLES.type_id.create(
sv.sformatf("TABLES[%0d]", i))
self.TABLES.append(rslave_tables)
self.DMA_RAM = mem_slave_DMA_RAM.type_id.create("DMA_RAM")
#UVMResourceDb.set("REG::" + self.DMA_RAM.get_full_name() + ".*", "NO_REG_TESTS", 1, self)
# configure
self.ID.configure(self, None, "ID")
self.ID.build()
self.INDEX.configure(self, None, "INDEX")
self.INDEX.build()
for i in range(len(self.SESSION)):
self.SESSION[i].configure(self, None,
sv.sformatf("SESSION[%0d]", i))
self.SESSION[i].build()
for i in range(len(self.TABLES)):
self.TABLES[i].configure(self, None, sv.sformatf("TABLES[%0d]", i))
self.TABLES[i].build()
self.DATA.configure(self.INDEX, self.TABLES, self, None)
self.DATA.build()
self.DMA_RAM.configure(self, "")
# define default map
self.default_map = self.create_map("default_map", 0x0, 4,
UVM_LITTLE_ENDIAN)
self.default_map.add_reg(self.ID, 0x0, "RW")
self.default_map.add_reg(self.INDEX, 0x20, "RW")
self.default_map.add_reg(self.DATA, 0x24, "RW")
for i in range(len(self.SESSION)):
self.SESSION[i].map(self.default_map, 0x1000 + 16 * i)
self.default_map.add_mem(self.DMA_RAM, 0x2000, "RW")
# field handle aliases
self.REVISION_ID = self.ID.REVISION_ID
self.CHIP_ID = self.ID.CHIP_ID
self.PRODUCT_ID = self.ID.PRODUCT_ID
def run_phase(self, phase):
if self.add_objection:
phase.raise_objection(self)
num = ""
uvm_info("producer", "Starting with packet " + str(self.num_packets),
UVM_MEDIUM)
for count in range(self.num_packets):
p = self.proto.clone()
num = str(count)
p.set_name(self.get_name() + "-" + num)
p.set_initiator(self)
if self.recording_detail != UVM_NONE:
p.enable_recording(self.get_tr_stream("packet_stream"))
p.randomize()
uvm_info("producer", sv.sformatf("Sending %s", p.get_name()),
UVM_MEDIUM)
if self.uvm_report_enabled(UVM_HIGH, UVM_INFO, ""):
p.print()
yield self.out.put(p)
yield Timer(10, "NS")
uvm_info("producer", "Exiting.", UVM_MEDIUM)
if self.add_objection:
phase.drop_objection(self)
def check_phase(self, phase):
if self.drv.nitems != (2 * NUM_SEQS * NUM_LOOPS):
self.error = True
self.uvm_report_error(
'env',
sv.sformatf("nitems: Exp %0d, Got %0d", NUM_SEQS * NUM_LOOPS,
self.drv.nitems))
def run_phase(self, phase):
# Check config from initial block
if self.l1.data != self.corr_data1:
uvm_error("BADCFG", sv.sformatf("Expected l1.data = %0d, got %0d",
self.corr_data1, self.l1.data))
if self.l2.data != self.corr_data2:
uvm_error("BADCFG", sv.sformatf("Expected l2.data = %0d, got %0d",
self.corr_data2, self.l2.data))
if self.l1.str != self.l2.str and self.l1.str != "hi":
uvm_error("BADCFG", sv.sformatf(
"Expected l1.str = \"hi\" and l2.str = \"hi\", got l1.str = \"%s\" and l2.str = \"%s\"",
self.l1.str, self.l2.str))
phase.raise_objection(self)
yield Timer(10)
#10 $display("%0t: %s HI", $time, get_full_name());
phase.drop_objection(self)
def extract_phase(self, phase):
if self.apb.mon.num_items > 0 and self.apb.mon.errors == 0:
self.all_ok = True
else:
uvm_error(
"SYS_ENV_ERR",
sv.sformatf("num_items: %0d, mon.errors: %0d",
self.apb.mon.num_items, self.apb.mon.errors))
def body(self):
req = None # REQ req
rsp = None # RSP rsp
uvm_info("sequenceA", "Starting sequence", UVM_MEDIUM)
for i in range(NUM_LOOPS):
#req = uvm_create(req, self.m_sequencer)
uvm_info("sequenceA", "Starting item " + str(i), UVM_MEDIUM)
req = bus_req("my_req")
yield Timer(10, "NS")
req.addr = (self.my_id * NUM_LOOPS) + i
req.data = self.my_id + i + 55
req.op = BUS_WRITE
if self.m_sequencer is None:
raise Exception("Null sequencer CRASH")
# uvm_send(req)
yield self.start_item(req)
yield self.finish_item(req)
uvm_info("sequenceA", "getting response1 for " + str(i),
UVM_MEDIUM)
rsp = []
yield self.get_response(rsp)
uvm_info(
"sequenceA",
"got response1 for " + str(i) + ": " + rsp[0].convert2string(),
UVM_MEDIUM)
#uvm_create(req)
req = bus_req("my_req")
req.addr = (self.my_id * NUM_LOOPS) + i
req.data = 0
req.op = BUS_READ
#uvm_send(req)
yield self.start_item(req)
yield self.finish_item(req)
uvm_info("sequenceA", "getting response2 for " + str(i),
UVM_MEDIUM)
rsp = []
yield self.get_response(rsp)
rsp = rsp[0]
if rsp.data != (self.my_id + i + 55):
uvm_error(
"SequenceA",
sv.sformatf(
"Error, addr: %0d, expected data: %0d, actual data: %0d",
req.addr, req.data, rsp.data))
uvm_info("sequenceA", "Finishing sequence", UVM_MEDIUM)
def put(self, p):
print("consumer put() called with count " + str(self.count))
yield self.lock.get()
self.count += 1
self.accept_tr(p)
yield Timer(10, "NS")
# #10
self.begin_tr(p)
# #30;
yield Timer(10, "NS")
self.end_tr(p)
uvm_info("consumer", sv.sformatf("Received %0s local_count=%0d",
p.get_name(),self.count), UVM_MEDIUM)
if self.uvm_report_enabled(UVM_HIGH,UVM_INFO,""):
p.print()
self.lock.put()
def convert2string(self):
s = sv.sformatf("pair : %s, %s",
self.first.convert2string(), self.second.convert2string())
return s
def convert2string(self):
return sv.sformatf("addr=%0h data=%0h", self.addr, self.data)
def do_print(self, printer):
printer.print_array_header("a", len(self.a))
for i in range(len(self.a)):
printer.print_field(sv.sformatf("a[%0d]", i), self.a[i], 32,
UVM_HEX, "[")
printer.print_array_footer()
async def do_bus_read(self, rw, driver, adapter):
"""
Function: do_bus_read()
Perform a bus read operation
Args:
rw (UVMRegItem): the item to be driven
driver (BusDriver): the Cocotb driver to use
adapter (DVRegAdapter): the bus adapter to use
"""
addrs = [] # uvm_reg_addr_t[$]
system_map = self.get_root_map()
bus_width = self.get_n_bytes()
byte_en = int(''.join(['1' for bit in range(bus_width)]))
map_info = None
size = 0
n_bits = 0
skip = 0
lsb = 0
curr_byte = 0
n_access_extra = 0
n_access = 0
n_bits_init = 0
accesses = [] # uvm_reg_bus_op[$]
[map_info, n_bits_init, lsb,
skip] = self.Xget_bus_infoX(rw, map_info, n_bits_init, lsb, skip)
# Need a copy as this will be modified later
addrs = map_info.addr.copy()
# if a memory, adjust addresses based on offset
if (rw.element_kind == UVM_MEM):
for i in range(len(addrs)):
addrs[i] = addrs[i] + map_info.mem_range.stride * rw.offset
for val_idx in range(len(rw.value)):
rw.value[val_idx] = 0
# /* calculate byte_enables */
if (rw.element_kind == UVM_FIELD):
temp_be = 0
ii = 0
n_access_extra = lsb % (bus_width * 8)
n_access = n_access_extra + n_bits_init
temp_be = n_access_extra
while (temp_be >= 8):
# byte_en[ii] = 0
byte_en = sv.clear_bit(byte_en, ii)
ii += 1
temp_be -= 8
temp_be += n_bits_init
while (temp_be > 0):
# byte_en[ii] = 1
byte_en = sv.set_bit(byte_en, ii)
ii += 1
temp_be -= 8
byte_en &= (1 << ii) - 1
for i in range(skip):
addrs.pop_front()
while addrs.size() > (int(n_bits_init / (bus_width * 8)) + 1):
addrs.pop_back()
#end
curr_byte = 0
n_bits = n_bits_init
accesses = []
for i in range(len(addrs)):
rw_access = UVMRegBusOp()
uvm_debug(
self.get_type_name(),
sv.sformatf("Reading address 'h%0h via map \"%s\"...",
addrs[i], self.get_full_name()),
UVM_VERB_MEM_MAP)
if (rw.element_kind == UVM_FIELD):
#for (int z=0;z<bus_width;z++)
for z in range(bus_width):
# rw_access.byte_en[z] = byte_en[curr_byte+z]
bit_val = sv.get_bit(byte_en, curr_byte + z)
rw_access.byte_en = sv.set_bit(rw_access.byte_en, z,
bit_val)
rw_access.kind = rw.kind
rw_access.addr = addrs[i]
rw_access.data = curr_byte
rw_access.byte_en = byte_en
rw_access.n_bits = n_bits
if (n_bits > bus_width * 8):
rw_access.n_bits = bus_width * 8
accesses.append(rw_access)
curr_byte += bus_width
n_bits -= bus_width * 8
# if set utilize the order policy
if (self.policy is not None):
self.policy.order(accesses)
# perform accesses
for i in range(len(accesses)):
rw_access = accesses[i] # uvm_reg_bus_op
bus_req = None # uvm_sequence_item
data = 0 # uvm_reg_data_logic_t
curr_byte_ = 0
curr_byte_ = rw_access.data
rw_access.data = 0
adapter.m_set_item(rw)
bus_req = adapter.reg2bus(rw_access)
adapter.m_set_item(None)
if bus_req is None:
uvm_fatal(
"RegMem", "adapter [" + adapter.get_name() +
"] didnt return a bus transaction")
# Call the driver, must stall
await self.m_driver.busy_send(bus_req)
if adapter.provides_responses:
bus_rsp = None # uvm_sequence_item
op = 0 # uvm_access_e
# TODO: need to test for right trans type, if not put back in q
await rw.parent.get_base_response(bus_rsp)
rw_access = adapter.bus2reg(bus_rsp, rw_access)
else:
adapter.bus2reg(bus_req, rw_access)
data = rw_access.data & (
(1 << bus_width * 8) - 1) # mask the upper bits
rw.status = rw_access.status
# TODO
#if (rw.status == UVM_IS_OK && (^data) === 1'bx):
uvm_debug(
self.get_type_name(),
sv.sformatf("Read 0x%h at 0x%h via map %s: %s...",
data, addrs[i], self.get_full_name(),
str(rw.status)), UVM_VERB_MEM_MAP)
if (rw.status == UVM_NOT_OK):
break
rw.value[val_idx] |= data << curr_byte_ * 8
for i in range(len(addrs)):
addrs[i] = addrs[i] + map_info.mem_range.stride
if (rw.element_kind == UVM_FIELD):
rw.value[val_idx] = (rw.value[val_idx] >>
(n_access_extra)) & ((1 << size) - 1)
async def do_bus_write(self, rw, driver, adapter):
"""
Function: do_bus_write()
Perform a bus write operation
Args:
rw (UVMRegItem): the item to be driven
driver (BusDriver): the Cocotb driver to use
adapter (DVRegAdapter): the bus adapter to use
"""
addrs = []
system_map = self.get_root_map()
bus_width = self.get_n_bytes()
byte_en = int(''.join(['1' for bit in range(bus_width)]), 2)
map_info = None
n_bits = 0
lsb = 0
skip = 0
curr_byte = 0
n_access_extra = 0
n_access = 0
n_bits_init = 0
[map_info, n_bits_init, lsb,
skip] = self.Xget_bus_infoX(rw, map_info, n_bits_init, lsb, skip)
addrs = map_info.addr.copy()
# if a memory, adjust addresses based on offset
if rw.element_kind == UVM_MEM:
for i in range(len(addrs)):
addrs[i] = addrs[i] + map_info.mem_range.stride * rw.offset
for val_idx in range(len(rw.value)):
value = rw.value[val_idx]
# /* calculate byte_enables */
if rw.element_kind == UVM_FIELD:
temp_be = 0
idx = 0
n_access_extra = lsb % (bus_width * 8)
n_access = n_access_extra + n_bits_init
temp_be = n_access_extra
value = value << n_access_extra
while temp_be >= 8:
byte_en = sv.clear_bit(byte_en, idx)
idx += 1
temp_be -= 8
temp_be += n_bits_init
while temp_be > 0:
byte_en = sv.set_bit(byte_en, idx)
# byte_en[idx] = 1
idx += 1
temp_be -= 8
byte_en &= (1 << idx) - 1
for i in range(skip):
addrs.pop_front()
while len(addrs) > (int(n_bits_init / (bus_width * 8)) + 1):
addrs.pop_back()
curr_byte = 0
n_bits = n_bits_init
accesses = []
for i in range(len(addrs)):
rw_access = UVMRegBusOp()
data = (value >> (curr_byte * 8)) & ((1 <<
(bus_width * 8)) - 1)
uvm_debug(
self.get_type_name(),
sv.sformatf("Writing 0x%0h at 0x%0h via map %s...", data,
addrs[i], rw.map.get_full_name()),
UVM_VERB_MEM_MAP)
if rw.element_kind == UVM_FIELD:
for z in range(bus_width):
bit_val = sv.get_bit(byte_en, curr_byte + z)
# rw_access.byte_en[z] = byte_en[curr_byte+z]
rw_access.byte_en = sv.set_bit(rw_access.byte_en, z,
bit_val)
rw_access.kind = rw.kind
rw_access.addr = addrs[i]
rw_access.data = data
#rw_access.n_bits = (n_bits > bus_width*8) ? bus_width*8 : n_bits
rw_access.n_bits = n_bits
if (n_bits > bus_width * 8):
rw_access.n_bits = bus_width * 8
rw_access.byte_en = byte_en
accesses.append(rw_access)
curr_byte += bus_width
n_bits -= bus_width * 8
# if set utilize the order policy
if (self.policy is not None):
self.policy.order(accesses)
# perform accesses
for i in range(len(accesses)):
rw_access = accesses[i] # uvm_reg_bus_op
bus_req = None # uvm_sequence_item
adapter.m_set_item(rw)
bus_req = adapter.reg2bus(rw_access)
adapter.m_set_item(None)
if bus_req is None:
uvm_fatal(
"RegMem", "adapter [" + adapter.get_name() +
"] didnt return a bus transaction")
# Drive the transaction
await self.m_driver.busy_send(bus_req)
if adapter.provides_responses:
bus_rsp = None # uvm_sequence_item
op = None # uvm_access_e
# TODO: need to test for right trans type, if not put back in q
await rw.parent.get_base_response(bus_rsp)
rw_access = adapter.bus2reg(bus_rsp, rw_access)
else:
rw_access = adapter.bus2reg(bus_req, rw_access)
if rw_access is None:
uvm_error(
"ADAPTER_BUS2REG_NONE",
sv.sformatf(
"Adapter %s" + " returned None for RW item %s",
adapter.get_name(), bus_req.convert2string()))
rw.status = rw_access.status
uvm_debug(
self.get_type_name(),
sv.sformatf("Wrote 0x%0h at 0x%0h via map %s: %s...",
rw_access.data, addrs[i],
rw.map.get_full_name(), rw.status),
UVM_VERB_MEM_MAP)
if rw.status == UVM_NOT_OK:
break
for i in range(len(addrs)):
addrs[i] = addrs[i] + map_info.mem_range.stride
def convert2string(self):
return sv.sformatf("op %s, status=%s",
bus_trans.convert2string(self),
str(self.status))
def convert2string(self):
return sv.sformatf("op %s: addr=%03x, data=%02x", str(self.op),
self.addr, self.data)
