def run_pex(self, a, output=None): if output == None: output = OPTS.openram_temp + a.name + ".pex.netlist" tempspice = "{0}{1}.sp".format(OPTS.openram_temp,a.name) tempgds = "{0}{1}.gds".format(OPTS.openram_temp,a.name) import verify result=verify.run_pex(a.name, tempgds, tempspice, output=output, final_verification=False) if result != 0: self.fail("PEX ERROR: {}".format(a.name)) return output
def run_pex(self, a, output=None): tempspice = "{}.sp".format(a.name) tempgds = "{}.gds".format(a.name) a.gds_write("{0}{1}".format(OPTS.openram_temp, tempgds)) import verify result = verify.run_pex(a.name, tempgds, tempspice, final_verification=False) if result != 0: self.fail("PEX ERROR: {}".format(a.name)) return output
def func_test(self, bank_num): import sram import tech debug.info(1, "Testing timing for sample 1bit, 16words SRAM with 1 bank") OPTS.check_lvsdrc = False OPTS.use_pex = True s = sram.sram(word_size=OPTS.word_size, num_words=OPTS.num_words, num_banks=OPTS.num_banks, name="test_sram1") OPTS.check_lvsdrc = True OPTS.use_pex = False tempspice = OPTS.openram_temp + "temp.sp" tempgds = OPTS.openram_temp + "temp.gds" s.sp_write(tempspice) s.gds_write(tempgds) self.assertFalse(verify.run_drc(s.name, tempgds)) self.assertFalse(verify.run_lvs(s.name, tempgds, tempspice)) self.assertFalse( verify.run_pex(s.name, tempgds, tempspice, output=OPTS.openram_temp + "temp_pex.sp")) import sp_file stimulus_file = OPTS.openram_temp + "stimulus.sp" a_stimulus = sp_file.sp_file(stimulus_file) self.write_stimulus(a_stimulus) simulator_file = OPTS.openram_temp + "simulator.sp" a_simulator = sp_file.sp_file(simulator_file) self.write_simulator(a_simulator) result_file = OPTS.openram_temp + "result" import os if OPTS.spice_name == "hspice": cmd = "hspice -mt 2 -i {0} > {1} ".format(simulator_file, result_file) else: cmd = "ngspice -b -i {0} > {1} ".format(simulator_file, result_file) os.system(cmd) import re sp_result = open(result_file, "r") contents = sp_result.read() key = "vr1" val = re.search(r"{0}(\s*)=(\s*)(\d*(.).*)(\s*)(from)".format(key), contents) val = val.group(3) value1 = float(self.convert_voltage_unit(val)) key = "vr2" val = re.search(r"{0}(\s*)=(\s*)(\d*(.).*)(\s*)(from)".format(key), contents) val = val.group(3) value2 = float(self.convert_voltage_unit(val)) self.assertTrue(round(value1) > 0.5 * tech.spice["supply_voltage"]) self.assertTrue(round(value2) < 0.5 * tech.spice["supply_voltage"]) OPTS.check_lvsdrc = True
def save(self): """ Save all the output files while reporting time to do it as well. """ # Save the spice file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".sp" debug.print_raw("SP: Writing to {0}".format(spname)) self.sp_write(spname) functional(self.s, os.path.basename(spname), cycles=200, output_path=OPTS.output_path) print_time("Spice writing", datetime.datetime.now(), start_time) if not OPTS.netlist_only: # Write the layout start_time = datetime.datetime.now() gdsname = OPTS.output_path + self.s.name + ".gds" debug.print_raw("GDS: Writing to {0}".format(gdsname)) self.gds_write(gdsname) if OPTS.check_lvsdrc: verify.write_drc_script(cell_name=self.s.name, gds_name=os.path.basename(gdsname), extract=True, final_verification=True, output_path=OPTS.output_path) print_time("GDS", datetime.datetime.now(), start_time) # Create a LEF physical model start_time = datetime.datetime.now() lefname = OPTS.output_path + self.s.name + ".lef" debug.print_raw("LEF: Writing to {0}".format(lefname)) self.lef_write(lefname) print_time("LEF", datetime.datetime.now(), start_time) # Save the LVS file start_time = datetime.datetime.now() lvsname = OPTS.output_path + self.s.name + ".lvs.sp" debug.print_raw("LVS: Writing to {0}".format(lvsname)) self.lvs_write(lvsname) if not OPTS.netlist_only and OPTS.check_lvsdrc: verify.write_lvs_script(cell_name=self.s.name, gds_name=os.path.basename(gdsname), sp_name=os.path.basename(lvsname), final_verification=True, output_path=OPTS.output_path) print_time("LVS writing", datetime.datetime.now(), start_time) # Save the extracted spice file if OPTS.use_pex: start_time = datetime.datetime.now() # Output the extracted design if requested pexname = OPTS.output_path + self.s.name + ".pex.sp" spname = OPTS.output_path + self.s.name + ".sp" verify.run_pex(self.s.name, gdsname, spname, output=pexname) sp_file = pexname print_time("Extraction", datetime.datetime.now(), start_time) else: # Use generated spice file for characterization sp_file = spname # Save a functional simulation file # Characterize the design start_time = datetime.datetime.now() from characterizer import lib debug.print_raw("LIB: Characterizing... ") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) # Write the config file start_time = datetime.datetime.now() from shutil import copyfile copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py') debug.print_raw( "Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) print_time("Config", datetime.datetime.now(), start_time) # Write the datasheet start_time = datetime.datetime.now() from datasheet_gen import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" debug.print_raw("Datasheet: Writing to {0}".format(dname)) datasheet_gen.datasheet_write(dname) print_time("Datasheet", datetime.datetime.now(), start_time) # Write a verilog model start_time = datetime.datetime.now() vname = OPTS.output_path + self.s.name + ".v" debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) print_time("Verilog", datetime.datetime.now(), start_time) # Write out options if specified if OPTS.output_extended_config: start_time = datetime.datetime.now() oname = OPTS.output_path + OPTS.output_name + "_extended.py" debug.print_raw("Extended Config: Writing to {0}".format(oname)) self.extended_config_write(oname) print_time("Extended Config", datetime.datetime.now(), start_time)
def save(self): """ Save all the output files while reporting time to do it as well. """ if not OPTS.netlist_only: # Create a LEF physical model start_time = datetime.datetime.now() lefname = OPTS.output_path + self.s.name + ".lef" debug.print_raw("LEF: Writing to {0}".format(lefname)) self.lef_write(lefname) print_time("LEF", datetime.datetime.now(), start_time) # Write the layout start_time = datetime.datetime.now() gdsname = OPTS.output_path + self.s.name + ".gds" debug.print_raw("GDS: Writing to {0}".format(gdsname)) self.gds_write(gdsname) print_time("GDS", datetime.datetime.now(), start_time) # Save the spice file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".sp" debug.print_raw("SP: Writing to {0}".format(spname)) self.sp_write(spname) print_time("Spice writing", datetime.datetime.now(), start_time) # Save the LVS file start_time = datetime.datetime.now() spname = OPTS.output_path + self.s.name + ".lvs" debug.print_raw("LVS: Writing to {0}".format(spname)) self.lvs_write(spname) print_time("LVS writing", datetime.datetime.now(), start_time) # Save the extracted spice file if OPTS.use_pex: import verify start_time = datetime.datetime.now() # Output the extracted design if requested sp_file = OPTS.output_path + "temp_pex.sp" verify.run_pex(self.s.name, gdsname, spname, output=sp_file) print_time("Extraction", datetime.datetime.now(), start_time) else: # Use generated spice file for characterization sp_file = spname # Characterize the design start_time = datetime.datetime.now() from characterizer import lib debug.print_raw("LIB: Characterizing... ") lib(out_dir=OPTS.output_path, sram=self.s, sp_file=sp_file) print_time("Characterization", datetime.datetime.now(), start_time) # Write the config file start_time = datetime.datetime.now() from shutil import copyfile copyfile(OPTS.config_file, OPTS.output_path + OPTS.output_name + '.py') debug.print_raw( "Config: Writing to {0}".format(OPTS.output_path + OPTS.output_name + '.py')) print_time("Config", datetime.datetime.now(), start_time) # Write the datasheet start_time = datetime.datetime.now() from datasheet_gen import datasheet_gen dname = OPTS.output_path + self.s.name + ".html" debug.print_raw("Datasheet: Writing to {0}".format(dname)) datasheet_gen.datasheet_write(dname) print_time("Datasheet", datetime.datetime.now(), start_time) # Write a verilog model start_time = datetime.datetime.now() vname = OPTS.output_path + self.s.name + ".v" debug.print_raw("Verilog: Writing to {0}".format(vname)) self.verilog_write(vname) print_time("Verilog", datetime.datetime.now(), start_time)
num_banks=num_banks, name=OPTS.output_name) last_time = print_time("SRAM creation", datetime.datetime.now(), last_time) # Output the files for the resulting SRAM spname = OPTS.output_path + s.name + ".sp" print("SP: Writing to {0}".format(spname)) s.sp_write(spname) last_time = print_time("Spice writing", datetime.datetime.now(), last_time) # Output the extracted design sram_file = spname if OPTS.use_pex: sram_file = OPTS.output_path + "temp_pex.sp" verify.run_pex(s.name, gdsname, spname, output=sram_file) # Characterize the design from characterizer import lib libname = OPTS.output_path + s.name + ".lib" print("LIB: Writing to {0}".format(libname)) if OPTS.analytical_delay: print("Using analytical delay models (no characterization)") else: if OPTS.spice_name != "": print("Performing simulation-based characterization with {}".format( OPTS.spice_name)) if OPTS.trim_netlist: print("Trimming netlist to speed up characterization.") lib.lib(libname, s, sram_file) last_time = print_time("Characterization", datetime.datetime.now(), last_time)
def runTest(self): OPTS.tech_name = "freepdk45" globals.init_openram("config_20_{0}".format(OPTS.tech_name)) OPTS.spice_name = "hspice" OPTS.analytical_delay = False OPTS.netlist_only = True OPTS.trim_netlist = False OPTS.check_lvsdrc = True # This is a hack to reload the characterizer __init__ with the spice version from importlib import reload import characterizer reload(characterizer) from characterizer import worst_case if not OPTS.spice_exe: debug.error("Could not find {} simulator.".format(OPTS.spice_name), -1) word_size, num_words, num_banks = 2, 16, 1 from sram import sram from sram_config import sram_config c = sram_config(word_size=word_size, num_words=num_words, num_banks=num_banks) c.words_per_row = 1 c.recompute_sizes() debug.info( 1, "Testing the timing different bitecells inside a {}bit, {} words SRAM with {} bank" .format(word_size, num_words, num_banks)) s = sram(c, name="sram1") sp_netlist_file = OPTS.openram_temp + "temp.sp" s.sp_write(sp_netlist_file) if OPTS.use_pex: gdsname = OPTS.output_path + s.name + ".gds" s.gds_write(gdsname) import verify reload(verify) # Output the extracted design if requested sp_pex_file = OPTS.output_path + s.name + "_pex.sp" verify.run_pex(s.name, gdsname, sp_netlist_file, output=sp_pex_file) sp_sim_file = sp_pex_file debug.info( 1, "Performing spice simulations with backannotated spice file.") else: sp_sim_file = sp_netlist_file debug.info(1, "Performing spice simulations with spice netlist.") corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0]) wc = worst_case(s.s, sp_sim_file, corner) import tech loads = [tech.spice["msflop_in_cap"] * 4] slews = [tech.spice["rise_time"] * 2] probe_address = "1" * s.s.addr_size probe_data = s.s.word_size - 1 wc.analyze(probe_address, probe_data, slews, loads) globals.end_openram()