def visit_Case(self, node):
condition = tuple([self.visit(c)
for c in node.cond]) if node.cond else [None]
statement = to_tuple(self.visit(node.statement))
when = vtypes.When(*condition)
when = when(*statement)
return when
def mkROMDefinition(name,
values,
size,
datawidth,
sync=False,
with_enable=False):
if not sync and with_enable:
raise ValueError('Async ROM cannot have enable signals')
m = Module(name)
clk = m.Input('CLK') if sync else None
addr = m.Input('addr', size)
if with_enable:
enable = m.Input('enable')
val = m.OutputReg('val', datawidth)
if clk is not None:
alw = m.Always(vtypes.Posedge(clk))
else:
alw = m.Always()
patterns = [
vtypes.When(i)(val(v, blk=not sync)) for i, v in enumerate(values)
]
body = vtypes.Case(addr)(*patterns)
if with_enable:
body = vtypes.If(enable)(body)
alw(body)
return m
def _get_when_statement(self, index):
body = []
body.extend(self.body[index])
for dst, cond, else_dst in self.jump[index]:
self._add_mark(dst)
if else_dst is not None:
self._add_mark(else_dst)
body.append(self._to_state_assign(dst, cond, else_dst))
return vtypes.When(self._cond_case(index))(*body)
def mkROMDefinition(name, values, size, datawidth, sync=False):
m = Module(name)
clk = m.Input('CLK') if sync else None
addr = m.Input('addr', size)
val = m.OutputReg('val', datawidth)
if clk is not None:
alw = m.Always(vtypes.Posedge(clk))
else:
alw = m.Always()
patterns = [
vtypes.When(i)(val(v, blk=not sync)) for i, v in enumerate(values)
]
alw(vtypes.Case(addr)(*patterns))
return m
def _get_delayed_when_statement(self, index, delay):
return vtypes.When(
self._cond_case(index))(*self.delayed_body[delay][index])
def visit_When(self, node):
condition = self.visit(node.condition)
statement = self.visit(node.statement)
ret = vtypes.When(*condition)
ret.statement = statement
return ret
