def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiSlave(m, 'myaxi', clk, rst)
myaxi.disable_read()
fsm = FSM(m, 'fsm', clk, rst)
# write address
addr, counter, valid = myaxi.pull_write_request(cond=fsm)
fsm.If(valid).goto_next()
# write data
sum = m.Reg('sum', 32, initval=0)
data, mask, valid, last = myaxi.pull_write_data(counter, cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().If(last).goto_next()
fsm.If(sum < 4096).goto_init()
fsm.If(sum >= 4096).goto_next()
expected_sum = 4096
fsm(Systask('display', "sum=%d expected_sum=%d", sum, expected_sum))
fsm.goto_next()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
sum = m.OutputReg('sum', 32, initval=0)
myaxi = axi.AxiSlave(m, 'myaxi', clk, rst)
fsm = FSM(m, 'fsm', clk, rst)
# request
addr, counter, readvalid, writevalid = myaxi.pull_request(cond=fsm)
rdata = m.Reg('rdata', 32, initval=0)
fsm.If(readvalid)(rdata(addr >> 2))
fsm.If(writevalid).goto(100)
fsm.If(readvalid).goto_next()
# read
ack, last = myaxi.push_read_data(rdata, counter, cond=fsm)
fsm.If(ack)(rdata(rdata + 1))
fsm.If(last).goto_next()
fsm.goto_init()
# write
fsm.set_index(100)
data, mask, valid, last = myaxi.pull_write_data(counter, cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().If(last).goto_next()
fsm.goto_init()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiSlave(m, 'myaxi', clk, rst)
myaxi.disable_write()
fsm = FSM(m, 'fsm', clk, rst)
# read address
addr, counter, valid = myaxi.pull_read_request(cond=fsm)
fsm.If(valid).goto_next()
# read rdata
rdata = m.Reg('rdata', 32, initval=512)
fsm.goto_next()
ack, last = myaxi.push_read_data(rdata, counter, cond=fsm)
fsm.If(ack)(
rdata(rdata + 512)
)
fsm.If(last).goto_next()
fsm.If(rdata < 4096).goto_init()
fsm.If(rdata >= 4096).goto_next()
seq = Seq(m, 'seq', clk, rst)
sum = m.Reg('sum', 32, initval=0)
expected_sum = (512 + 512 * 7) * 7 // 2
seq.If(myaxi.rdata.rvalid, myaxi.rdata.rready)(
sum(sum + myaxi.rdata.rdata)
)
fsm(
Systask('display', "sum=%d expected_sum=%d", sum, expected_sum)
)
fsm.goto_next()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
sum = m.OutputReg('sum', 32, initval=0)
myaxi = axi.AxiSlave(m, 'myaxi', clk, rst)
myaxi.disable_read()
fsm = FSM(m, 'fsm', clk, rst)
# write address
addr, counter, valid = myaxi.pull_write_request_counter(cond=fsm)
fsm.If(valid).goto_next()
# write data
data, mask, valid, last = myaxi.pull_write_data(counter, cond=fsm)
fsm.If(valid)(sum(sum + data))
fsm.Then().If(last).goto_next()
fsm.goto_init()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
myaxi = axi.AxiSlave(m, 'myaxi', clk, rst)
myaxi.disable_write()
fsm = FSM(m, 'fsm', clk, rst)
# read address
addr, counter, valid = myaxi.pull_read_request_counter(cond=fsm)
rdata = m.Reg('rdata', 32, initval=0)
fsm.If(valid)(rdata(addr >> 2))
fsm.If(valid).goto_next()
# read rdata
ack, last = myaxi.push_read_data(rdata, counter, cond=fsm)
fsm.If(ack)(rdata(rdata + 1))
fsm.If(last).goto_next()
fsm.goto_init()
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
# AXI ports
slave = axi.AxiSlave(m, 'slave', clk, rst)
master = axi.AxiMaster(m, 'master', clk, rst)
# a, b: source, c: result
ram_a = ram.SyncRAMManager(m, 'ram_a', clk, rst, numports=1)
ram_b = ram.SyncRAMManager(m, 'ram_b', clk, rst, numports=1)
ram_c = ram.SyncRAMManager(m, 'ram_c', clk, rst, numports=1)
read_fsm = FSM(m, 'read_fsm', clk, rst)
write_fsm = FSM(m, 'write_fsm', clk, rst)
df = dataflow.DataflowManager(m, clk, rst)
# df.enable_draw_graph()
read_fsm.goto_next()
row_count = m.Reg('row_count', 32, initval=0)
read_fsm(row_count(0))
# wait for slave request
slave_addr, slave_counter, slave_valid = slave.pull_write_request(
cond=read_fsm)
read_fsm.If(slave_valid).goto_next()
data, mask, valid, last = slave.pull_write_data(slave_counter,
cond=read_fsm)
read_fsm.If(valid).goto_next()
write_fsm.If(read_fsm).goto_next()
# computation
master_addr = 1024 * 2
ram_addr = 0
length = 16
dma_done = master.dma_read(ram_b,
master_addr,
ram_addr,
length,
cond=read_fsm)
read_fsm.If(dma_done).goto_next()
comp_start = read_fsm.current
master_addr = 1024
ram_addr = 0
length = 16
dma_done = master.dma_read(ram_a,
master_addr,
ram_addr,
length,
cond=read_fsm)
read_fsm.If(dma_done).goto_next()
adata, alast, adone = ram_a.read_dataflow(0,
ram_addr,
length,
cond=read_fsm)
bdata, blast, bdone = ram_b.read_dataflow(0,
ram_addr,
length,
cond=read_fsm)
read_fsm.goto_next()
mul = adata * bdata
mul_count = df.Counter(maxval=length)
wcond = mul_count == 0
cdata = df.Iadd(mul, reset=wcond.prev(1))
read_fsm(row_count.inc())
read_fsm.If(row_count < length - 1).goto(comp_start)
read_fsm.If(row_count == length - 1).goto_next()
done = ram_c.write_dataflow(0,
0,
cdata,
length,
cond=write_fsm,
when=wcond)
write_fsm.goto_next()
write_fsm.If(done).goto_next()
master_addr = 1024 * 3
dma_done = master.dma_write(ram_c,
master_addr,
ram_addr,
length,
cond=write_fsm)
write_fsm.If(dma_done).goto_next()
read_fsm.If(write_fsm).goto_init()
write_fsm.goto_init()
seq = Seq(m, 'seq', clk, rst)
seq.If(ram_c[0].wenable)(Systask('display', '[%d]<-%d', ram_c[0].addr,
ram_c[0].wdata))
return m
def mkMain():
m = Module('main')
clk = m.Input('CLK')
rst = m.Input('RST')
slave = axi.AxiSlave(m, 'slave', clk, rst)
master = axi.AxiMaster(m, 'master', clk, rst)
ram_a = bram.Bram(m, 'ram_a', clk, rst, numports=1)
ram_b = bram.Bram(m, 'ram_b', clk, rst, numports=1)
ram_c = bram.Bram(m, 'ram_c', clk, rst, numports=1)
fsm = FSM(m, 'fsm', clk, rst)
# wait for slave request
slave_addr, slave_counter, slave_valid = slave.pull_write_request(cond=fsm)
fsm.If(slave_valid).goto_next()
data, mask, valid, last = slave.pull_write_data(slave_counter, cond=fsm)
fsm.If(valid).goto_next()
# computation
master_addr = 1024
ram_addr = 0
length = 64
dma_done = master.dma_read(ram_a, master_addr, ram_addr, length, cond=fsm)
fsm.If(dma_done).goto_next()
master_addr = 1024 * 2
dma_done = master.dma_read(ram_b, master_addr, ram_addr, length, cond=fsm)
fsm.If(dma_done).goto_next()
adata, alast, adone = ram_a.read_dataflow(0, ram_addr, length, cond=fsm)
bdata, blast, bdone = ram_b.read_dataflow(0, ram_addr, length, cond=fsm)
cdata = adata + bdata
done = ram_c.write_dataflow(0, ram_addr, cdata, length, cond=fsm)
fsm.goto_next()
fsm.If(done).goto_next()
master_addr = 1024 * 3
dma_done = master.dma_write(ram_c, master_addr, ram_addr, length, cond=fsm)
fsm.If(dma_done).goto_next()
# checksum
sum = m.Reg('sum', 32, initval=0)
expected_sum = (((1024 + 1024 + 63) * 64 // 2) +
((1024 * 2 + 1024 * 2 + 63) * 64 // 2))
seq = Seq(m, 'seq', clk, rst)
seq.If(fsm.state == 0)(sum(0))
seq.If(master.wdata.wvalid,
master.wdata.wready)(sum(sum + master.wdata.wdata))
seq.If(master.wdata.wvalid, master.wdata.wready,
master.wdata.wlast).Delay(1)(Systask('display',
"sum=%d expected_sum=%d", sum,
expected_sum))
fsm.If(master.wdata.wvalid, master.wdata.wready,
master.wdata.wlast).Delay(1).goto_next()
# return the checksum
slave_addr, slave_counter, slave_valid = slave.pull_read_request(cond=fsm)
fsm.If(slave_valid).goto_next()
ack, last = slave.push_read_data(sum, slave_counter, cond=fsm)
fsm.If(last).goto_next()
# repeat
fsm.goto_init()
return m
