def imm_val_c(self):
with vsc.implies(self.imm_type.inside(vsc.rangelist(imm_t.NZIMM, imm_t.NZUIMM))):
self.imm[5:0] != 0
with vsc.implies(self.instr_name == riscv_instr_name_t.C_LUI):
self.imm[31:5] == 0
with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_SRAI,
riscv_instr_name_t.C_SRLI,
riscv_instr_name_t.C_SLLI))):
self.imm[31:5] == 0
with vsc.implies(self.instr_name == riscv_instr_name_t.C_ADDI4SPN):
self.imm[1:0] == 0
def imm_c(self):
with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.SLLIW,
riscv_instr_name_t.SRLIW,
riscv_instr_name_t.SRAIW))):
self.imm[11:5] == 0
with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.SLLI,
riscv_instr_name_t.SRLI,
riscv_instr_name_t.SRAI))):
with vsc.implies(self.XLEN == 32):
self.imm[11:5] == 0
with vsc.implies(self.XLEN != 32):
self.imm[11:6] == 0
def unique_c(self):
# with vsc.foreach(self.arr, idx=True) as i:
# self.arr[i] == i
with vsc.foreach(self.arr, idx=True) as i:
with vsc.foreach(self.arr, idx=True) as j:
with vsc.implies(i != j):
self.arr[i] != self.arr[j]
def ab_c(self):
self.a == 5
with vsc.implies(self.a == 1):
self.b == 1
with vsc.implies(self.a == 2):
self.b == 2
with vsc.implies(self.a == 3):
self.b == 4
with vsc.implies(self.a == 4):
self.b == 8
with vsc.implies(self.a == 5):
self.b == 16
def no_hint_illegal_instr_c(self):
with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_ADDI,
riscv_instr_name_t.C_ADDIW,
riscv_instr_name_t.C_LI,
riscv_instr_name_t.C_LUI,
riscv_instr_name_t.C_SLLI,
riscv_instr_name_t.C_SLLI64,
riscv_instr_name_t.C_LQSP,
riscv_instr_name_t.C_LDSP,
riscv_instr_name_t.C_MV,
riscv_instr_name_t.C_ADD,
riscv_instr_name_t.C_LWSP))):
self.rd != riscv_reg_t.ZERO
with vsc.implies(self.instr_name == riscv_instr_name_t.C_JR):
self.rs1 != riscv_reg_t.ZERO
with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_ADD,
riscv_instr_name_t.C_MV))):
self.rs2 != riscv_reg_t.ZERO
with vsc.implies(self.instr_name == riscv_instr_name_t.C_LUI):
self.rd != riscv_reg_t.SP
def rvc_csr_c(self):
# Registers specified by the three-bit rs1’, rs2’, and rd’
with vsc.implies(self.format.inside(vsc.rangelist(riscv_instr_format_t.CIW_FORMAT,
riscv_instr_format_t.CL_FORMAT,
riscv_instr_format_t.CS_FORMAT,
riscv_instr_format_t.CB_FORMAT,
riscv_instr_format_t.CA_FORMAT))):
with vsc.implies(self.has_rs1 == 1):
self.rs1.inside(vsc.rangelist(riscv_reg_t.S0, riscv_reg_t.S1, riscv_reg_t.A0,
riscv_reg_t.A1, riscv_reg_t.A2, riscv_reg_t.A3,
riscv_reg_t.A4, riscv_reg_t.A5))
with vsc.implies(self.has_rs2 == 1):
self.rs2.inside(vsc.rangelist(riscv_reg_t.S0, riscv_reg_t.S1, riscv_reg_t.A0,
riscv_reg_t.A1, riscv_reg_t.A2, riscv_reg_t.A3,
riscv_reg_t.A4, riscv_reg_t.A5))
with vsc.implies(self.has_rd == 1):
self.rd.inside(vsc.rangelist(riscv_reg_t.S0, riscv_reg_t.S1, riscv_reg_t.A0,
riscv_reg_t.A1, riscv_reg_t.A2, riscv_reg_t.A3,
riscv_reg_t.A4, riscv_reg_t.A5))
# _ADDI16SP is only valid when rd == SP
with vsc.implies(self.instr_name == riscv_instr_name_t.C_ADDI16SP):
self.rd == riscv_reg_t.SP
with vsc.implies(self.instr_name.inside(vsc.rangelist(riscv_instr_name_t.C_JR,
riscv_instr_name_t.C_JALR))):
self.rs1 != riscv_reg_t.ZERO
self.rs2 == riscv_reg_t.ZERO
async def run_xfer(self):
channel = vsc.rand_uint32_t()
xfer_spec = XferSpec()
# Randomly select a channel not currently in use
with vsc.randomize_with(channel):
channel < self.n_channels
with vsc.foreach(self.active_channels, idx=True) as i:
with vsc.implies(i == channel):
self.active_channels[i] == False
print("channel: " + str(channel))
self.active_xfers += 1
self.active_channels[channel] = True
xfer_spec.randomize()
# TODO: program channel
ch = self.dma_regs.channel(int(channel))
sz = await ch.read_sz()
sz.chk_sz = xfer_spec.chksz
sz.tot_sz = xfer_spec.totsz
await ch.write_sz(sz)
csr = await ch.read_csr()
csr.ine_done = 1
csr.inc_src = xfer_spec.inc_src
csr.inc_dst = xfer_spec.inc_dst
print("INC_SRC: " + str(csr.inc_src) + " INC_DST: " + str(csr.inc_dst))
csr.en = 1
await ch.write_csr(csr)
await ch.write_src_addr(0x00000000 | int(channel) << 16)
await ch.write_dst_addr(0x80000000 | int(channel) << 16)
# TODO: start xfer
# Wait for completion
await self.done_ev[int(channel)].wait()
self.done_ev[int(channel)].clear()
# TODO: program and carry out transfer
# await cocotb.triggers.Timer(1, "us")
self.active_xfers -= 1
print("Channel " + str(channel) + " done " + str(self.active_xfers))
self.active_channels[channel] = False
self.n_complete += 1
pass
def hardwired_fld_c(self):
with vsc.implies(self.hard_wired == 1):
self.val == self.reset_val
def zero_reserved_field_c(self):
with vsc.implies(self.access_type == reg_field_access_t.WPRI):
self.val == 0
def jal_c(self):
with vsc.implies(self.XLEN != 32):
self.instr_name != riscv_instr_name_t.C_JAL