def __init__(self):
super().__init__()
self.num_of_avail_regs = vsc.uint32_t(10)
self.num_of_instr = vsc.rand_uint8_t()
self.init_val = vsc.randsz_list_t(vsc.rand_bit_t(rcs.XLEN - 1))
self.init_val_type = vsc.randsz_list_t(vsc.enum_t(int_numeric_e))
self.init_instr = []
def __init__(self):
self.addr = rand_bit_t(16)
self.read_write = rand_enum_t(ubus_read_write_enum)
self.size = rand_bit_t(32)
self.data = vsc.randsz_list_t(vsc.uint8_t())
self.wait_state = vsc.randsz_list_t(vsc.bit_t(4))
self.error_pos = rand_bit_t(32)
self.transmit_delay = rand_bit_t(32)
self.master = ""
self.slave = ""
def __init__(self):
super().__init__()
self.num_amo = vsc.rand_uint32_t()
self.num_mixed_instr = vsc.rand_uint32_t()
self.offset = vsc.randsz_list_t(vsc.int32_t())
self.rs1_reg = vsc.randsz_list_t(vsc.enum_t(riscv_reg_t))
self.num_of_rs1_reg = vsc.rand_int32_t()
self.data_page_id = vsc.uint32_t()
self.max_offset = vsc.uint32_t()
self.XLEN = vsc.uint32_t(rcs.XLEN)
# User can specify a small group of available registers to generate various hazard condition
self.avail_regs = vsc.randsz_list_t(vsc.enum_t(riscv_reg_t))
def __init__(self):
# Number of programs in the call stack
self.program_cnt = vsc.int_t(10)
# Handles of all programs
self.program_h = []
# Maximum call stack level
self.max_stack_level = vsc.int_t(50)
# Call stack level of each program
self.stack_level = vsc.randsz_list_t(vsc.bit_t(11))
def __init__(self):
self.instr_list = []
self.instr_cnt = 0
self.label = ""
# User can specify a small group of available registers to generate various hazard condition
self.avail_regs = vsc.randsz_list_t(vsc.enum_t(riscv_reg_t))
# Some additional reserved registers that should not be used as rd register
# by this instruction stream
self.reserved_rd = vsc.list_t(vsc.enum_t(riscv_reg_t))
self.hart = 0
def __init__(self):
self.loop_cnt_reg = vsc.randsz_list_t(vsc.enum_t(my_e))
self.loop_limit_reg = vsc.randsz_list_t(vsc.enum_t(my_e))
self.loop_init_val = vsc.randsz_list_t(vsc.uint32_t())
self.loop_step_val = vsc.randsz_list_t(vsc.uint32_t())
self.loop_limit_val = vsc.randsz_list_t(vsc.uint32_t())
self.num_of_nested_loop = vsc.rand_bit_t(3)
self.num_of_instr_in_loop = vsc.rand_uint32_t()
self.branch_type = vsc.randsz_list_t(vsc.enum_t(my_e))
def __init__(self):
super().__init__()
self.loop_cnt_reg = vsc.randsz_list_t(vsc.enum_t(riscv_reg_t))
self.loop_limit_reg = vsc.randsz_list_t(vsc.enum_t(riscv_reg_t))
self.loop_init_val = vsc.randsz_list_t(vsc.int32_t())
self.loop_step_val = vsc.randsz_list_t(vsc.int32_t())
self.loop_limit_val = vsc.randsz_list_t(vsc.int32_t())
self.num_of_nested_loop = vsc.rand_bit_t(3)
self.num_of_instr_in_loop = vsc.rand_int32_t(0)
self.branch_type = vsc.randsz_list_t(vsc.enum_t(riscv_instr_name_t))
self.loop_init_instr = []
self.loop_update_instr = []
self.loop_branch_instr = []
self.loop_branch_target_instr = []
# Aggregated loop instruction stream
self.loop_instr = []
def __init__(self):
super().__init__()
self.vals = vsc.randsz_list_t(vsc.enum_t(my_e))
def __init__(self):
self.fixed = vsc.rand_list_t(vsc.bit_t(8), sz=4)
self.dynamic = vsc.randsz_list_t(vsc.bit_t(8))
self.queue = vsc.randsz_list_t(vsc.bit_t(8))
def __init__(self):
self.temp = vsc.randsz_list_t(vsc.uint8_t())
self.a = vsc.list_t(vsc.uint8_t(), init=[1, 2, 3, 5, 6, 7, 8])
def __init__(self):
self.l = vsc.randsz_list_t(vsc.uint16_t())
def __init__(self):
self.v1 = vsc.randsz_list_t(vsc.rand_bit_t(8))
self.v2 = vsc.randsz_list_t(vsc.rand_bit_t(8))
def __init__(self):
super().__init__()
self.num_of_nested_loop = vsc.rand_bit_t(8)
self.loop_init_val = vsc.randsz_list_t(vsc.uint8_t())
def __init__(self):
self.my_l = vsc.randsz_list_t(uint8_t())
def __init__(self):
self.offset = vsc.randsz_list_t(vsc.int32_t())
self.reg = vsc.randsz_list_t(vsc.enum_t(reg_t))
self.num_of_regs = vsc.rand_uint32_t()
self.reserved_regs = vsc.randsz_list_t(vsc.enum_t(reg_t))
self.max_offset = vsc.rand_uint32_t()
def __init__(self):
self.l = vsc.randsz_list_t(vsc.uint8_t())
self.a = vsc.rand_uint8_t()
def __init__(self):
self.s = 7
self.a = vsc.randsz_list_t(vsc.rand_uint8_t())
self.b = vsc.rand_list_t(vsc.enum_t(my_e), 5)
def __init__(self):
# ---------------------------------------------------------------------------
# Random instruction generation settings
# ---------------------------------------------------------------------------
# Instruction count of the main program
self.main_program_instr_cnt = vsc.rand_int32_t()
# Instruction count of each sub-program
self.sub_program_instr_cnt = vsc.randsz_list_t(vsc.int32_t())
# Instruction count of the debug rom
self.debug_program_instr_cnt = 0
# Instruction count of debug sub-programs
self.debug_sub_program_instr_cnt = vsc.randsz_list_t(vsc.int32_t())
# Pattern of data section: RAND_DATA, ALL_ZERO, INCR_VAL
self.data_page_pattern = vsc.rand_enum_t(data_pattern_t)
# Initialization of the vregs
# SAME_VALUES_ALL_ELEMS - Using vmv.v.x to fill all the elements of the vreg with
# the same value as the one in the GPR selected
# RANDOM_VALUES_VMV - Using vmv.v.x + vslide1up.vx to randomize the contents
# of each vector element
# RANDOM_VALUES_LOAD - Using vle.v, same approach as RANDOM_VALUES_VMV but more
# efficient for big VLEN
self.vreg_init_method = vreg_init_method_t.RANDOM_VALUES_VMV
# Maximum directed instruction stream sequence count
self.max_directed_instr_stream_seq = 20
self.init_delegation()
self.argv = self.parse_args()
self.args_dict = vars(self.argv)
global rcs
rcs = import_module("pygen_src.target." + self.argv.target +
".riscv_core_setting")
# Dict for delegation configuration for each exception and interrupt
# When the bit is 1, the corresponding delegation is enabled.
# TODO
self.m_mode_exception_delegation = {}
self.s_mode_exception_delegation = {}
self.m_mode_interrupt_delegation = {}
self.s_mode_interrupt_delegation = {}
# init_privileged_mode default to MACHINE_MODE
# TODO: remove defult machine_mode once all modes get supported
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
self.mstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.mie = vsc.rand_bit_t(rcs.XLEN - 1)
self.sstatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.sie = vsc.rand_bit_t(rcs.XLEN - 1)
self.ustatus = vsc.rand_bit_t(rcs.XLEN - 1)
self.uie = vsc.rand_bit_t(rcs.XLEN - 1)
# Key fields in xSTATUS
# Memory protection bits
self.mstatus_mprv = vsc.rand_bit_t(1)
self.mstatus_mxr = vsc.rand_bit_t(1)
self.mstatus_sum = vsc.rand_bit_t(1)
self.mstatus_tvm = vsc.rand_bit_t(1)
self.mstatus_fs = vsc.rand_bit_t(2)
self.mstatus_vs = vsc.rand_bit_t(2)
self.mtvec_mode = vsc.rand_enum_t(mtvec_mode_t)
# TVEC alignment
# This value is the log_2 of the byte-alignment of TVEC.BASE field
# As per RISC-V privileged spec, default will be set to 2 (4-byte aligned)
self.tvec_alignment = vsc.rand_uint32_t(self.argv.tvec_alignment)
# Floating point rounding mode
self.fcsr_rm = vsc.rand_enum_t(f_rounding_mode_t)
# Enable sfence.vma instruction
self.enable_sfence = vsc.rand_bit_t(1)
# Reserved register
# Reserved for various hardcoded routines
self.gpr = vsc.rand_list_t(vsc.enum_t(riscv_reg_t), sz=4)
# Used by any DCSR operations inside of the debug rom.
# Also used by the PMP generation.
self.scratch_reg = vsc.rand_enum_t(riscv_reg_t)
# Reg used exclusively by the PMP exception handling routine.
# Can overlap with the other GPRs used in the random generation,
# as PMP exception handler is hardcoded and does not include any
# random instructions.
self.pmp_reg = vsc.rand_enum_t(riscv_reg_t)
# Use a random register for stack pointer/thread pointer
self.sp = vsc.rand_enum_t(riscv_reg_t)
self.tp = vsc.rand_enum_t(riscv_reg_t)
self.ra = vsc.rand_enum_t(riscv_reg_t)
# Options for privileged mode CSR checking
# Below checking can be made optional as the ISS implementation
# could be different with the processor.
self.check_misa_init_val = 0
self.check_xstatus = 1
# Virtual address translation is on for this test
self.virtual_addr_translation_on = vsc.rand_bit_t(1)
# Commenting out for now
# vector_cfg = riscv_vector_cfg # TODO
# pmp_cfg = riscv_pmp_cfg # TODO
# Stack section word length
self.stack_len = 5000
# -----------------------------------------------------------------------------
# User space memory region and stack setting
# -----------------------------------------------------------------------------
self.mem_region = vsc.list_t(mem_region_t())
self.amo_region = vsc.list_t(mem_region_t())
self.s_mem_region = vsc.list_t(mem_region_t())
self.mem_region.extend([
mem_region_t(name="region_0", size_in_bytes=4096, xwr=8),
mem_region_t(name="region_1", size_in_bytes=4096, xwr=8)
])
self.amo_region.extend(
[mem_region_t(name="amo_0", size_in_bytes=64, xwr=8)])
self.s_mem_region.extend([
mem_region_t(name="s_region_0", size_in_bytes=4096, xwr=8),
mem_region_t(name="s_region_1", size_in_bytes=4096, xwr=8)
])
# Kernel Stack section word length
self.kernel_stack_len = 4000
# Number of instructions for each kernel program
self.kernel_program_instr_cnt = 400
# List of all the main implemented CSRs that the boot privilege mode cannot access
# e.g. these CSRs are in higher privilege modes - access should raise an exception
self.invalid_priv_mode_csrs = []
# -----------------------------------------------------------------------------
# Command line options or control knobs
# -----------------------------------------------------------------------------
# Main options for RISC-V assembly program generation
# Number of sub-programs per test
self.num_of_sub_program = self.argv.num_of_sub_program
self.instr_cnt = self.argv.instr_cnt
self.num_of_tests = self.argv.num_of_tests
# For tests doesn't involve load/store, the data section generation could be skipped
self.no_data_page = self.argv.no_data_page
# Options to turn off some specific types of instructions
self.no_branch_jump = self.argv.no_branch_jump # No branch/jump instruction
self.no_load_store = self.argv.no_load_store # No load/store instruction
self.no_csr_instr = self.argv.no_csr_instr # No csr instruction
self.no_ebreak = self.argv.no_ebreak # No ebreak instruction
self.no_dret = self.argv.no_dret # No dret instruction
self.no_fence = self.argv.no_fence # No fence instruction
self.no_wfi = self.argv.no_wfi # No WFI instruction
self.enable_unaligned_load_store = self.argv.enable_unaligned_load_store
self.illegal_instr_ratio = self.argv.illegal_instr_ratio
self.hint_instr_ratio = self.argv.hint_instr_ratio
# Number of harts to be simulated, must be <= NUM_HARTS
if self.argv.num_of_harts is None:
self.num_of_harts = rcs.NUM_HARTS
else:
self.num_of_harts = self.argv.num_of_harts
# Use SP as stack pointer
self.fix_sp = vsc.bit_t(1)
self.fix_sp = self.argv.fix_sp
# Use push/pop section for data pages
self.use_push_data_section = self.argv.use_push_data_section
# Directed boot privileged mode, u, m, s
self.boot_mode_opts = self.argv.boot_mode
# self.isa = self.argv.isa
if self.boot_mode_opts:
logging.info("Got boot mode option - {}".format(
self.boot_mode_opts))
if self.boot_mode_opts == "m":
self.init_privileged_mode = privileged_mode_t.MACHINE_MODE
elif self.boot_mode_opts == "s":
self.init_privileged_mode = privileged_mode_t.SUPERVISOR_MODE
elif self.boot_mode_opts == "u":
self.init_privileged_mode = privileged_mode_t.USER_MODE
else:
logging.error("Illegal boot mode option - {}".format(
self.boot_mode_opts))
self.enable_page_table_exception = self.argv.enable_page_table_exception
self.no_directed_instr = self.argv.no_directed_instr
self.asm_test_suffix = self.argv.asm_test_suffix
# Enable interrupt bit in MSTATUS (MIE, SIE, UIE)
self.enable_interrupt = self.argv.enable_interrupt
self.enable_nested_interrupt = self.argv.enable_nested_interrupt
# We need a separate control knob for enabling timer interrupts, as Spike
# throws an exception if xIE.xTIE is enabled
self.enable_timer_irq = self.argv.enable_timer_irq
# Generate a bare program without any init/exit/error handling/page table routines
# The generated program can be integrated with a larger program.
# Note that the bare mode program is not expected to run in standalone mode
self.bare_program_mode = self.argv.bare_program_mode
# Enable accessing illegal CSR instruction
# - Accessing non-existence CSR
# - Accessing CSR with wrong privileged mode
self.enable_illegal_csr_instruction = self.argv.enable_illegal_csr_instruction
# Enable accessing CSRs at an invalid privilege level
self.enable_access_invalid_csr_level = self.argv.enable_access_invalid_csr_level
# Enable misaligned instruction (caused by JALR instruction)
self.enable_misaligned_instr = self.argv.enable_misaligned_instr
# Enable some dummy writes to main system CSRs (xSTATUS/xIE) at beginning of test
# to check repeated writes
self.enable_dummy_csr_write = self.argv.enable_dummy_csr_write
self.randomize_csr = self.argv.randomize_csr
# sfence support
self.allow_sfence_exception = self.argv.allow_sfence_exception
# Interrupt/Exception Delegation
self.no_delegation = self.argv.no_delegation
self.force_m_delegation = self.argv.force_m_delegation
self.force_s_delegation = self.argv.force_s_delegation
self.support_supervisor_mode = 0 # TODO
self.disable_compressed_instr = vsc.uint8_t(1)
self.disable_compressed_instr = self.argv.disable_compressed_instr
self.require_signature_addr = self.argv.require_signature_addr
if self.require_signature_addr:
self.signature_addr = int(self.argv.signature_addr, 16)
else:
self.signature_addr = 0xdeadbeef
# Enable a full or empty debug_rom section.
# Full debug_rom will contain random instruction streams.
# Empty debug_rom will contain just dret instruction and will return immediately.
# Will be empty by default.
self.gen_debug_section = self.argv.gen_debug_section
# Enable generation of a directed sequence of instructions containing
# ebreak inside the debug_rom.
# Disabled by default.
self.enable_ebreak_in_debug_rom = self.argv.enable_ebreak_in_debug_rom
# Enable setting dcsr.ebreak(m/s/u)
self.set_dcsr_ebreak = self.argv.set_dcsr_ebreak
# Number of sub programs in the debug rom
self.num_debug_sub_program = self.argv.num_debug_sub_program
# Enable debug single stepping
self.enable_debug_single_step = self.argv.enable_debug_single_step
# Number of single stepping iterations
self.single_step_iterations = vsc.rand_uint32_t()
# Enable mstatus.tw bit - causes u-mode WFI to raise illegal instruction exceptions
self.set_mstatus_tw = self.argv.set_mstatus_tw
# Enable users to set mstatus.mprv to enable privilege checks on memory accesses.
self.set_mstatus_mprv = vsc.bit_t(1)
self.set_mstatus_mprv = self.argv.set_mstatus_mprv
# Stack space allocated to each program, need to be enough to store necessary context
# Example: RA, SP, T0
self.min_stack_len_per_program = 10 * (rcs.XLEN // 8)
self.max_stack_len_per_program = 16 * (rcs.XLEN // 8)
# Maximum branch distance, avoid skipping large portion of the code
self.max_branch_step = 20
# Reserved registers
self.reserved_regs = vsc.list_t(vsc.enum_t(riscv_reg_t))
# Floating point support
self.enable_floating_point = vsc.bit_t(1)
self.enable_floating_point = self.argv.enable_floating_point
# Vector extension support
self.enable_vector_extension = self.argv.enable_vector_extension
# Only generate vector instructions
self.vector_instr_only = vsc.bit_t(1)
# Bit manipulation extension support
self.enable_b_extension = self.argv.enable_b_extension
self.enable_bitmanip_groups = self.argv.enable_bitmanip_groups
# -----------------------------------------------------------------------------
# Command line options for instruction distribution control
# -----------------------------------------------------------------------------
self.dist_control_mode = 0
self.category_dist = {}
self.march_isa = self.argv.march_isa
if len(self.march_isa) != 0:
rcs.supported_isa.append(self.march_isa)
if riscv_instr_group_t.RV32C not in rcs.supported_isa:
self.disable_compressed_instr = 1
self.setup_instr_distribution()
self.get_invalid_priv_lvl_csr()
# Helpers fields to build the vsc constraints
self.supported_interrupt_mode = vsc.list_t(vsc.enum_t(mtvec_mode_t))
self.XLEN = vsc.uint32_t()
self.SATP_MODE = vsc.enum_t(satp_mode_t)
self.init_privil_mode = vsc.enum_t(privileged_mode_t)
self.init_privil_mode = self.init_privileged_mode
self.supported_interrupt_mode = rcs.supported_interrupt_mode
self.XLEN = rcs.XLEN
self.SATP_MODE = rcs.SATP_MODE
self.tvec_ceil = vsc.uint32_t()
self.tvec_ceil = math.ceil(math.log2((self.XLEN * 4) / 8))
