def test_compile_project_verilog(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix", library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog")
     simif.compile_project(project, vhdl_standard="2008")
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path)
     run_command.assert_called_once_with([
         join('prefix', 'vlog'), '-quiet', '-sv2k12', '-lc', library_cfg,
         '-work', 'lib', 'file.v', '-l', 'lib'
     ])
Beispiel #2
0
 def test_compile_project_system_verilog(self, process, check_output):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.sv", "")
     project.add_source_file("file.sv", "lib", file_type="systemverilog")
     simif.compile_project(project)
     process.assert_any_call(
         [join("prefix", "vlib"), "lib", "lib_path"],
         cwd=self.output_path,
         env=simif.get_env(),
     )
     process.assert_called_with(
         [join("prefix", "vmap"), "lib", "lib_path"],
         cwd=self.output_path,
         env=simif.get_env(),
     )
     check_output.assert_called_once_with(
         [
             join("prefix", "vlog"),
             "-quiet",
             "-lc",
             library_cfg,
             "-sv2k12",
             "-work",
             "lib",
             "file.sv",
             "-l",
             "lib",
         ],
         env=simif.get_env(),
     )
Beispiel #3
0
 def test_compile_project_vhdl_2008(self, process, check_output):
     simif = RivieraProInterface(prefix="prefix",
                                 output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd",
                             "lib",
                             file_type="vhdl",
                             vhdl_standard=VHDL.standard("2008"))
     simif.compile_project(project)
     process.assert_any_call(
         [join("prefix", "vlib"), "lib", "lib_path"],
         cwd=self.output_path,
         env=simif.get_env(),
     )
     process.assert_called_with(
         [join("prefix", "vmap"), "lib", "lib_path"],
         cwd=self.output_path,
         env=simif.get_env(),
     )
     check_output.assert_called_once_with(
         [
             join("prefix", "vcom"),
             "-quiet",
             "-j",
             self.output_path,
             "-2008",
             "-work",
             "lib",
             "file.vhd",
         ],
         env=simif.get_env(),
     )
    def test_compile_project_coverage(self, process, check_output):
        library_cfg = join(self.output_path, "library.cfg")

        for file_type, coverage_off in product(["vhdl", "verilog"],
                                               [False, True]):
            check_output.reset_mock()

            simif = RivieraProInterface(prefix="prefix",
                                        output_path=self.output_path,
                                        coverage="bes")

            project = Project()
            project.add_library("lib", "lib_path")

            if file_type == "vhdl":
                file_name = "file.vhd"
            else:
                file_name = "file.v"

            write_file(file_name, "")
            source_file = project.add_source_file(file_name,
                                                  "lib",
                                                  file_type=file_type)

            if coverage_off:
                covargs = []
                source_file.set_compile_option("disable_coverage", True)
            else:
                covargs = ['-coverage', 'bes']

            simif.compile_project(project)
            process.assert_any_call(
                [join("prefix", "vlib"), "lib", "lib_path"],
                cwd=self.output_path,
                env=simif.get_env())
            process.assert_called_with(
                [join("prefix", "vmap"), "lib", "lib_path"],
                cwd=self.output_path,
                env=simif.get_env())

            if file_type == "vhdl":
                check_output.assert_called_once_with(
                    [join('prefix', 'vcom'), '-quiet', '-j', self.output_path
                     ] + covargs + ['-2008', '-work', 'lib', 'file.vhd'],
                    env=simif.get_env())
            elif file_type == "verilog":
                check_output.assert_called_once_with(
                    [join('prefix', 'vlog'), '-quiet', '-lc', library_cfg] +
                    covargs + ['-work', 'lib', 'file.v', '-l', 'lib'],
                    env=simif.get_env())
            else:
                assert False
 def test_compile_project_vhdl_extra_flags(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix", library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     source_file = project.add_source_file("file.vhd",
                                           "lib",
                                           file_type="vhdl")
     source_file.set_compile_option("rivierapro.vcom_flags",
                                    ["custom", "flags"])
     simif.compile_project(project, vhdl_standard="2008")
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path)
     run_command.assert_called_once_with([
         join('prefix', 'vcom'), '-quiet', '-j', self.output_path, 'custom',
         'flags', '-2008', '-work', 'lib', 'file.vhd'
     ])
 def test_compile_project_vhdl(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl")
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
     run_command.assert_called_once_with(
         [join('prefix', 'vcom'),
          '-quiet',
          '-j',
          self.output_path,
          '-2008',
          '-work',
          'lib',
          'file.vhd'])
 def test_compile_project_vhdl(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl")
     simif.compile_project(project, vhdl_standard="2008")
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
     run_command.assert_called_once_with(
         [join('prefix', 'vcom'),
          '-quiet',
          '-j',
          self.output_path,
          '-2008',
          '-work',
          'lib',
          'file.vhd'])
 def test_compile_project_verilog(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog")
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
     run_command.assert_called_once_with([join('prefix', 'vlog'),
                                          '-quiet',
                                          '-sv2k12',
                                          '-lc',
                                          library_cfg,
                                          '-work',
                                          'lib',
                                          'file.v',
                                          '-l', 'lib'])
 def test_compile_project_vhdl_extra_flags(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     source_file = project.add_source_file("file.vhd", "lib", file_type="vhdl")
     source_file.set_compile_option("rivierapro.vcom_flags", ["custom", "flags"])
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
     run_command.assert_called_once_with([join('prefix', 'vcom'),
                                          '-quiet',
                                          '-j',
                                          self.output_path,
                                          'custom',
                                          'flags',
                                          '-2008',
                                          '-work',
                                          'lib',
                                          'file.vhd'])
 def test_compile_project_verilog_include(self, process, check_output):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog", include_dirs=["include"])
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path, env=None)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path, env=simif.get_env())
     check_output.assert_called_once_with([join('prefix', 'vlog'),
                                           '-quiet',
                                           '-lc',
                                           library_cfg,
                                           '-work',
                                           'lib',
                                           'file.v',
                                           '-l', 'lib',
                                           '+incdir+include'], env=simif.get_env())
 def test_compile_project_verilog_extra_flags(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     source_file = project.add_source_file("file.v", "lib", file_type="verilog")
     source_file.set_compile_option("rivierapro.vlog_flags", ["custom", "flags"])
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"], cwd=self.output_path)
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"], cwd=self.output_path)
     run_command.assert_called_once_with([join('prefix', 'vlog'),
                                          '-quiet',
                                          '-sv2k12',
                                          '-lc',
                                          library_cfg,
                                          'custom',
                                          'flags',
                                          '-work',
                                          'lib',
                                          'file.v',
                                          '-l', 'lib'])
    def test_compile_project_coverage(self, process, run_command):
        library_cfg = join(self.output_path, "library.cfg")

        for file_type in ["vhdl", "verilog"]:
            run_command.reset_mock()

            simif = RivieraProInterface(prefix="prefix",
                                        library_cfg=library_cfg,
                                        coverage="bes")

            project = Project()
            project.add_library("lib", "lib_path")

            if file_type == "vhdl":
                file_name = "file.vhd"
            else:
                file_name = "file.v"

            write_file(file_name, "")
            project.add_source_file(file_name, "lib", file_type=file_type)
            simif.compile_project(project)
            process.assert_any_call(
                [join("prefix", "vlib"), "lib", "lib_path"],
                cwd=self.output_path,
                env=simif.get_env())
            process.assert_called_with(
                [join("prefix", "vmap"), "lib", "lib_path"],
                cwd=self.output_path,
                env=simif.get_env())

            if file_type == "vhdl":
                run_command.assert_called_once_with([
                    join('prefix',
                         'vcom'), '-quiet', '-j', self.output_path, '-dbg',
                    '-coverage', 'bes', '-2008', '-work', 'lib', 'file.vhd'
                ],
                                                    env=simif.get_env())
            elif file_type == "verilog":
                run_command.assert_called_once_with([
                    join('prefix', 'vlog'), '-quiet', '-sv2k12', '-lc',
                    library_cfg, '-dbg', '-coverage', 'bes', '-work', 'lib',
                    'file.v', '-l', 'lib'
                ],
                                                    env=simif.get_env())
            else:
                assert False
Beispiel #13
0
 def test_compile_project_vhdl(self, process, check_output):
     simif = RivieraProInterface(prefix="prefix",
                                 output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl")
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path,
                             env=simif.get_env())
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path,
                                env=simif.get_env())
     check_output.assert_called_once_with([
         join('prefix', 'vcom'), '-quiet', '-j', self.output_path, '-2008',
         '-work', 'lib', 'file.vhd'
     ],
                                          env=simif.get_env())
 def test_compile_project_verilog(self, process, check_output):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix", library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v", "lib", file_type="verilog")
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path,
                             env=simif.get_env())
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path,
                                env=simif.get_env())
     check_output.assert_called_once_with([
         join('prefix', 'vlog'), '-quiet', '-lc', library_cfg, '-work',
         'lib', 'file.v', '-l', 'lib'
     ],
                                          env=simif.get_env())
Beispiel #15
0
 def test_compile_project_verilog_extra_flags(self, process, check_output):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     source_file = project.add_source_file("file.v",
                                           "lib",
                                           file_type="verilog")
     source_file.set_compile_option("rivierapro.vlog_flags",
                                    ["custom", "flags"])
     simif.compile_project(project)
     process.assert_any_call(
         [join("prefix", "vlib"), "lib", "lib_path"],
         cwd=self.output_path,
         env=simif.get_env(),
     )
     process.assert_called_with(
         [join("prefix", "vmap"), "lib", "lib_path"],
         cwd=self.output_path,
         env=simif.get_env(),
     )
     check_output.assert_called_once_with(
         [
             join("prefix", "vlog"),
             "-quiet",
             "-lc",
             library_cfg,
             "custom",
             "flags",
             "-work",
             "lib",
             "file.v",
             "-l",
             "lib",
         ],
         env=simif.get_env(),
     )
 def test_compile_project_verilog_define(self, process, run_command):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix", library_cfg=library_cfg)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     project.add_source_file("file.v",
                             "lib",
                             file_type="verilog",
                             defines={"defname": "defval"})
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path,
                             env=simif.get_env())
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path,
                                env=simif.get_env())
     run_command.assert_called_once_with([
         join('prefix', 'vlog'), '-quiet', '-sv2k12', '-lc', library_cfg,
         '-work', 'lib', 'file.v', '-l', 'lib', '+define+defname=defval'
     ],
                                         env=simif.get_env())
 def test_compile_project_vhdl(self, process, check_output):
     simif = RivieraProInterface(prefix="prefix",
                                 output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.vhd", "")
     project.add_source_file("file.vhd", "lib", file_type="vhdl")
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path, env=simif.get_env())
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path, env=simif.get_env())
     check_output.assert_called_once_with(
         [join('prefix', 'vcom'),
          '-quiet',
          '-j',
          self.output_path,
          '-2008',
          '-work',
          'lib',
          'file.vhd'], env=simif.get_env())
 def test_compile_project_verilog_extra_flags(self, process, check_output):
     library_cfg = join(self.output_path, "library.cfg")
     simif = RivieraProInterface(prefix="prefix",
                                 output_path=self.output_path)
     project = Project()
     project.add_library("lib", "lib_path")
     write_file("file.v", "")
     source_file = project.add_source_file("file.v", "lib", file_type="verilog")
     source_file.set_compile_option("rivierapro.vlog_flags", ["custom", "flags"])
     simif.compile_project(project)
     process.assert_any_call([join("prefix", "vlib"), "lib", "lib_path"],
                             cwd=self.output_path, env=simif.get_env())
     process.assert_called_with([join("prefix", "vmap"), "lib", "lib_path"],
                                cwd=self.output_path, env=simif.get_env())
     check_output.assert_called_once_with([join('prefix', 'vlog'),
                                           '-quiet',
                                           '-lc',
                                           library_cfg,
                                           'custom',
                                           'flags',
                                           '-work',
                                           'lib',
                                           'file.v',
                                           '-l', 'lib'], env=simif.get_env())