def __init__(self, interface, ADC='HMCAD1511', defaultDelayTap=0):
# interface => corr.katcp_wrapper.FpgaClient('10.1.0.23')
self.A_WB_R_LIST = [
self.WB_DICT.index(a) for a in self.WB_DICT if a != None
]
self.adcList = [0, 1, 2]
self.ramList = ['adc16_wb_ram0', 'adc16_wb_ram1', 'adc16_wb_ram2']
self.laneList = [0, 1, 2, 3, 4, 5, 6, 7]
self.curDelay = [[defaultDelayTap] * len(self.laneList)] * len(
self.adcList)
self.lmx = LMX2581(interface, 'lmx_ctrl')
self.clksw = HMC922(interface, 'adc16_use_synth')
self.ram = [WishBoneDevice(interface, name) for name in self.ramList]
if ADC not in ['HMCAD1511', 'HMCAD1520']:
raise ValueError("Invalid parameter")
if ADC == 'HMCAD1511':
self.adc = HMCAD1511(interface, 'adc16_controller')
else: # 'HMCAD1520'
self.adc = HMCAD1520(interface, 'adc16_controller')
# test pattern for clock aligning
pats = [0b10101010, 0b01010101, 0b00000000, 0b11111111]
mask = (1 << (self.RESOLUTION / 2)) - 1
ofst = self.RESOLUTION / 2
self.p1 = ((pats[0] & mask) << ofst) + (pats[3] & mask)
self.p2 = ((pats[1] & mask) << ofst) + (pats[2] & mask)
def __init__(self,
interface,
ADC='HMCAD1511',
ref=None,
resolution=8,
**kwargs):
self.RESOLUTION = 8
self.adc = None
self.lmx = None
self.clksw = None
self.ram = None
self.logger = kwargs.get('logger', logging.getLogger(__name__))
# Current delay tap settings for all IDELAYE2
self.curDelay = None
# interface => casperfpga.CasperFpga(hostname/ip)
self.interface = interface
self.A_WB_R_LIST = [
self.WB_DICT.index(a) for a in self.WB_DICT if a != None
]
self.adcList = [0, 1, 2]
self.ramList = ['adc16_wb_ram0', 'adc16_wb_ram1', 'adc16_wb_ram2']
self.laneList = [0, 1, 2, 3, 4, 5, 6, 7]
if resolution not in [8, 12, 14]:
self.logger.error("Invalid parameter")
raise ValueError("Invalid parameter")
else:
self.RESOLUTION = resolution
self.curDelay = np.zeros((len(self.adcList), len(self.laneList)))
if ref is not None:
self.lmx = LMX2581(interface, 'lmx_ctrl', fosc=ref)
else:
self.lmx = None
self.clksw = HMC922(interface, 'adc16_use_synth')
self.ram = [WishBoneDevice(interface, name) for name in self.ramList]
if ADC not in ['HMCAD1511', 'HMCAD1520']:
raise ValueError("Invalid parameter")
if ADC == 'HMCAD1511':
self.adc = HMCAD1511(interface, 'adc16_controller')
else: # 'HMCAD1520'
self.adc = HMCAD1520(interface, 'adc16_controller')
# test pattern for clock aligning
pats = [0b10101010, 0b01010101, 0b00000000, 0b11111111]
mask = (1 << (self.RESOLUTION / 2)) - 1
ofst = self.RESOLUTION / 2
self.p1 = ((pats[0] & mask) << ofst) + (pats[3] & mask)
self.p2 = ((pats[1] & mask) << ofst) + (pats[2] & mask)
def __init__(self, interface, resolution=8,defaultDelayTap=0):
# interface => corr.katcp_wrapper.FpgaClient('10.1.0.23')
self.A_WB_R_LIST = [self.WB_DICT.index(a) for a in self.WB_DICT if a != None]
self.adcList = [0, 1, 2]
self.ramList = ['adc16_wb_ram0', 'adc16_wb_ram1', 'adc16_wb_ram2']
self.laneList = [0, 1, 2, 3, 4, 5, 6, 7]
self.curDelay = dict(zip(self.adcList,[dict(zip(self.laneList,[defaultDelayTap]*len(self.laneList) ))]*len(self.adcList)))
self.lmx = LMX2581(interface,'lmx_ctrl')
self.clksw = HMC922(interface,'adc16_use_synth')
self.ram = [WishBoneDevice(interface,name) for name in self.ramList]
self.RESOLUTION = resolution
if self.RESOLUTION == 8:
self.adc = HMCAD1511(interface,'adc16_controller')
def __init__(self,
interface,
block_name,
bitwidth=64,
adrwidth=10,
ignore_trig=False,
ignore_we=True,
**kwargs):
if bitwidth not in [8, 16, 32, 64, 128]:
raise ValueError('Invalid parameter bitwidth.')
if adrwidth not in range(0, 30):
raise ValueError('Invalid parameter adrwidth.')
if ignore_trig not in [True, False]:
raise ValueError('Invalid parameter ignore_trig.')
if ignore_we not in [True, False]:
raise ValueError('Invalid parameter ignore_we.')
internal_prefix = ''
if kwargs is not None:
if 'internal_prefix' in kwargs:
internal_prefix = kwargs['internal_prefix']
self.ctrl = WishBoneDevice(interface,
block_name + internal_prefix + '_ctrl')
self.bram = WishBoneDevice(interface,
block_name + internal_prefix + '_bram')
self.stat = WishBoneDevice(interface,
block_name + internal_prefix + '_status')
self.ignore_trig = ignore_trig
self.ignore_we = ignore_we
self.bitwidth = bitwidth
self.adrwidth = adrwidth
count_bits = int(adrwidth + np.log2(self.bitwidth / 8))
done_bits = 1
self.MASK_COUNT = (1 << count_bits) - 1
self.MASK_DONE = 1 << count_bits
self.MASK_BUSY = 0xffffffff ^ self.MASK_COUNT ^ self.MASK_DONE
class Bitsnap(object):
""" A virtual oscilloscope that probes signals inside FPGA
interfce an instance of FpgaClient or CasperFpga
block_name the prefix name of the block, e.g. snapshot_eq
bitwidth the bit width of each sample
adrwidth 2**? number of samples being taken for each trigger
ignore_trig trigger() ignores external trigger signnal and trigger
the capture immediately
ignore_we ignore external capture signal and continuously capture
samples until hit the bottom of the BRAM
internal_prefix
Add a prefix to the name of internal wishbond devices.
This parameter is for the purpose of backward compatibility.
E.g. block_name='snap0', internal_prefix='_ss',
then the ctrl regiest inside 'snap0' is named
'snap0_ss_ctrl'.
E.g.
bs=bitsnap.Bitsnap(fpga,'snapshot_eq',64,10,False,True)
bs.trigger()
while bs.status()['DONE']==False:
pass
bs.read(nsample=512)
"""
ctrl = None
bram = None
stat = None
itf = None
bitwidth = None
adrwidth = None
def __init__(self,
interface,
block_name,
bitwidth=64,
adrwidth=10,
ignore_trig=False,
ignore_we=True,
**kwargs):
if bitwidth not in [8, 16, 32, 64, 128]:
raise ValueError('Invalid parameter bitwidth.')
if adrwidth not in range(0, 30):
raise ValueError('Invalid parameter adrwidth.')
if ignore_trig not in [True, False]:
raise ValueError('Invalid parameter ignore_trig.')
if ignore_we not in [True, False]:
raise ValueError('Invalid parameter ignore_we.')
internal_prefix = ''
if kwargs is not None:
if 'internal_prefix' in kwargs:
internal_prefix = kwargs['internal_prefix']
self.ctrl = WishBoneDevice(interface,
block_name + internal_prefix + '_ctrl')
self.bram = WishBoneDevice(interface,
block_name + internal_prefix + '_bram')
self.stat = WishBoneDevice(interface,
block_name + internal_prefix + '_status')
self.ignore_trig = ignore_trig
self.ignore_we = ignore_we
self.bitwidth = bitwidth
self.adrwidth = adrwidth
count_bits = int(adrwidth + np.log2(self.bitwidth / 8))
done_bits = 1
self.MASK_COUNT = (1 << count_bits) - 1
self.MASK_DONE = 1 << count_bits
self.MASK_BUSY = 0xffffffff ^ self.MASK_COUNT ^ self.MASK_DONE
def trigger(self):
cmd = (self.ignore_we << 2) + (self.ignore_trig << 1) + 0
self.ctrl._write(cmd)
self.ctrl._write(cmd | 0x1)
self.ctrl._write(cmd)
def read(self, nsample=None, nskip=0):
""" Read samples and return raw data
nsample number of samples to read
nskip read skips the first nskip samples
E.g.
mybs.read(nsample=512,nskip=128)
"""
if isinstance(nsample, int):
pass
else:
nsample = 1 << self.adrwidth
length = nsample * self.bitwidth / 8
skipaddr = nskip * self.bitwidth / 8
return self.bram._read(addr=skipaddr, size=length)
def status(self):
""" Status of the bitsnap module
status() returns a three pieces of information: (BUSY, DONE, COUNT).
BUSY busy status of the block
DONE ready status of the block
COUNT number of samples being captured
"""
data = self.stat._read()
s = {
'BUSY': (data & self.MASK_BUSY) != 0,
'DONE': (data & self.MASK_DONE) != 0,
'COUNT': data & self.MASK_COUNT
}
return s
def __init__(self, parent, device_name, device_info, initialise=False):
"""
Initialise SnapAdc Object
:param parent: Parent object creating the SnapAdc Object
:type parent: casperfpga.CasperFpga
:param device_name: Name of SnapAdc Object
:type device_name: str
:param device_info:
:type device_info: dict
:param intialise: Trigger ADC SerDes calibration.
:type initialise: Boolean - True/False
:return: None
example device_info = {'adc_resolution': '8',
'sample_rate': '200',
'snap_inputs': '12',
'tag': 'xps:snap_adc'}
"""
self.parent = parent
self.logger = parent.logger
self.name = device_name
self.device_info = device_info
try:
self.resolution = int(self.device_info['adc_resolution'])
self.sample_rate = float(self.device_info['sample_rate'])
self.num_channel = int(self.device_info['snap_inputs']) // 4
except:
print(self.device_info)
raise
if self.resolution == 8:
self.controller = HMCAD1511(parent,'adc16_controller')
else:
self.controller = HMCAD1520(parent, 'adc16_controller')
self.A_WB_R_LIST = [self.WB_DICT.index(a) for a in self.WB_DICT if a != None]
self.adcList = [0, 1, 2]
self.ramList = ['adc16_wb_ram0', 'adc16_wb_ram1', 'adc16_wb_ram2']
self.laneList = [0, 1, 2, 3, 4, 5, 6, 7]
if self.resolution not in [8,12,14]:
logger.error("Invalid resolution parameter")
raise ValueError("Invalid resolution parameter")
self.curDelay = [[0]*len(self.laneList)]*len(self.adcList)
# check if the design uses the on-board synthesizer -- can read from fpg 'SNAP' dict
if parent.devices['SNAP']['clk_src'] == 'sys_clk':
self.synth = LMX2581(parent, 'lmx_ctrl') # Use default FOSC ref setting
#self.synth_clk_rate = float(parent.devices['SNAP']['clk_rate'])
else:
self.synth = None
self.clksw = HMC922(parent,'adc16_use_synth')
self.ram = [WishBoneDevice(parent, name) for name in self.ramList]
# test pattern for clock aligning
pats = [0b10101010,0b01010101,0b00000000,0b11111111]
mask = (1 << (self.resolution / 2)) - 1
ofst = self.resolution / 2
self.p1 = ((pats[0] & mask) << ofst) + (pats[3] & mask)
self.p2 = ((pats[1] & mask) << ofst) + (pats[2] & mask)
if initialise:
self.init(sample_rate=self.sample_rate, num_channel=self.num_channel)