def split_ukernel_name(name):
common_name, target_name = name.split("__", 1)
common_parts = common_name.split("_")
param_spec = common_parts[-1].split("x")
mr = int(param_spec[0])
arch, isa = xnncommon.parse_target_name(target_name)
return mr, arch, isa
def split_ukernel_name(name):
match = re.match(
r"^xnn_(f16|f32)_v(add|div|max|min|mul|sub|addc|divc|rdivc|maxc|minc|mulc|subc|rsubc)_ukernel__(.+)_x(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
op_type = {
"add": "Add",
"div": "Div",
"max": "Max",
"min": "Min",
"mul": "Mul",
"sub": "Sub",
"addc": "AddC",
"divc": "DivC",
"rdivc": "RDivC",
"maxc": "MaxC",
"minc": "MinC",
"mulc": "MulC",
"subc": "SubC",
"rsubc": "RSubC",
}[match.group(2)]
batch_tile = int(match.group(4))
arch, isa = xnncommon.parse_target_name(target_name=match.group(3))
return op_type, batch_tile, arch, isa
def split_ukernel_name(name):
common_name, target_name = name.split("__", 1)
common_parts = common_name.split("_")
param_spec = common_parts[-1]
mr, nr = map(int, param_spec.split("x"))
arch, isa = xnncommon.parse_target_name(target_name)
return mr, nr, arch, isa
def split_ukernel_name(name):
match = re.match(
r"^xnn_(qs8|f16|f32)_v(add|div|max|min|mul|sqrdiff|sub|addc|divc|rdivc|maxc|minc|mulc|sqrdiffc|subc|rsubc)(_(minmax|relu))?_ukernel__(.+)_x(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
op_type = {
"add": "Add",
"div": "Div",
"max": "Max",
"min": "Min",
"mul": "Mul",
"sqrdiff": "SqrDiff",
"sub": "Sub",
"addc": "AddC",
"divc": "DivC",
"rdivc": "RDivC",
"maxc": "MaxC",
"minc": "MinC",
"mulc": "MulC",
"sqrdiffc": "SqrDiffC",
"subc": "SubC",
"rsubc": "RSubC",
}[match.group(2)]
batch_tile = int(match.group(6))
activation_type = match.group(4)
if activation_type is None:
activation_type = "LINEAR"
else:
activation_type = activation_type.upper()
arch, isa = xnncommon.parse_target_name(target_name=match.group(5))
return op_type, activation_type, batch_tile, arch, isa
def split_ukernel_name(name):
match = re.match(
r"^xnn_(u8|f16|f32)_v(abs|clamp|elu|hswish|lrelu|neg|relu|rndd|rndne|rndu|rndz|sigmoid|sqr|sqrt)_(fact_)?ukernel__(.+)_x(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
op_type = {
"abs": "Abs",
"clamp": "Clamp",
"elu": "ELU",
"hswish": "HardSwish",
"lrelu": "LeakyReLU",
"neg": "Negate",
"relu": "ReLU",
"rndd": "RoundDown",
"rndne": "RoundToNearestEven",
"rndz": "RoundTowardsZero",
"rndu": "RoundUp",
"sigmoid": "Sigmoid",
"sqr": "Square",
"sqrt": "SquareRoot",
}[match.group(2)]
batch_tile = int(match.group(5))
arch, isa = xnncommon.parse_target_name(target_name=match.group(4))
return op_type, batch_tile, arch, isa
def split_ukernel_name(name):
match = re.match(r"^xnn_(f16|f32)_vmulcaddc_ukernel_c(\d+)__(.+)$", name)
assert match is not None
cr = int(match.group(2))
arch, isa = xnncommon.parse_target_name(target_name=match.group(3))
return cr, arch, isa
def split_ukernel_name(name):
match = re.match(r"^xnn_(f16|f32)_raddexpminusmax_ukernel__(.+)_x(\d+)(_acc(\d+))?$", name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
elements_tile = int(match.group(3))
arch, isa = xnncommon.parse_target_name(target_name=match.group(2))
return elements_tile, arch, isa
def split_ukernel_name(name):
match = re.match(r"^xnn_(f16|f32)_prelu_ukernel__(.+)_(\d+)x(\d+)$", name)
assert match is not None
row_tile = int(match.group(3))
channel_tile = int(match.group(4))
arch, isa = xnncommon.parse_target_name(target_name=match.group(2))
return row_tile, channel_tile, arch, isa
def split_ukernel_name(name): match = re.match(r"^xnn_(f16|f32)_bilinear_ukernel__(.+)_c(\d+)$", name) assert match is not None channel_tile = int(match.group(3)) pixel_tile = 1 arch, isa = xnncommon.parse_target_name(target_name=match.group(2)) return channel_tile, pixel_tile, arch, isa
def split_ukernel_name(name):
match = re.match(r"^xnn_(f16|f32)_hswish_ukernel__(.+)_x(\d+)$", name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
batch_tile = int(match.group(3))
arch, isa = xnncommon.parse_target_name(target_name=match.group(2))
return batch_tile, arch, isa
def split_ukernel_name(name): match = re.match(r"^xnn_(f16|f32)_vmulcaddc(_(minmax))?_ukernel_c(\d+)__(.+)_(\d+)x$", name) assert match is not None channel_tile = int(match.group(4)) row_tile = int(match.group(6)) arch, isa = xnncommon.parse_target_name(target_name=match.group(5)) return channel_tile, row_tile, arch, isa
def split_ukernel_name(name):
common_name, target_name = name.split("__", 1)
common_parts = common_name.split("_")
param_spec = common_parts[-1]
assert param_spec.startswith("up")
cr, kr = map(int, param_spec[2:].split("x"))
arch, isa = xnncommon.parse_target_name(target_name)
return cr, kr, arch, isa
def split_ukernel_name(name):
match = re.match(r"^xnn_(x\d+)_transpose_ukernel__(\d+)x(\d+)_(.+)$", name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
tile_height = int(match.group(2))
tile_width = int(match.group(3))
arch, isa = xnncommon.parse_target_name(target_name=match.group(4))
return tile_height, tile_width, arch, isa
def split_ukernel_name(name):
match = re.match(r"^xnn_(f16|f32)_(sigmoid)_(fact_)?ukernel__(.+)_x(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
op_type = {
"sigmoid": "Sigmoid",
}[match.group(2)]
batch_tile = int(match.group(5))
arch, isa = xnncommon.parse_target_name(target_name=match.group(4))
return op_type, batch_tile, arch, isa
def split_ukernel_name(name):
match = re.match(
r"^xnn_(f16|f32|qs8|qu8)_(f16|f32|qs8|qu8)_vcvt_ukernel__(.+)_x(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
input_datatype = match.group(1)
output_datatype = match.group(2)
batch_tile = int(match.group(4))
arch, isa = xnncommon.parse_target_name(target_name=match.group(3))
return input_datatype, output_datatype, batch_tile, arch, isa
def split_ukernel_name(name):
match = re.match(
r"^xnn_(s8|u8|s16|f16|f32)_maxpool(_(minmax))?_ukernel_(\d+)p(\d+)x__(.+)_c(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
primary_tile = int(match.group(4))
incremental_tile = int(match.group(5))
channel_tile = int(match.group(7))
arch, isa = xnncommon.parse_target_name(target_name=match.group(6))
return primary_tile, incremental_tile, channel_tile, arch, isa
def split_ukernel_name(name):
common_name, target_name = name.split("__", 1)
common_parts = common_name.split("_")
param_spec = common_parts[-1]
assert param_spec.startswith("up")
cr, kr = map(int, param_spec[2:].split("x"))
arch, isa = xnncommon.parse_target_name(target_name)
requantization = common_parts[-3]
if requantization not in ["fp32", "gemmlowp", "rndnu"]:
requantization = None
return cr, kr, requantization, arch, isa
def split_ukernel_name(name):
match = re.match(r"^xnn_(qs8|qu8|f16|f32)_[p]?gavgpool(_(minmax))?_ukernel_((\d+)p)?(\d+)x__(.+)_c(\d+)(_acc(\d+))?$", name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
if match.group(4):
primary_tile = int(match.group(5))
incremental_tile = int(match.group(6))
else:
primary_tile = int(match.group(6))
incremental_tile = 0
channel_tile = int(match.group(8))
arch, isa = xnncommon.parse_target_name(target_name=match.group(7))
return primary_tile, incremental_tile, channel_tile, arch, isa
def split_ukernel_name(name):
common_name, target_name = name.split("__", 1)
common_parts = common_name.split("_")
param_spec = common_parts[-1]
if "s" in param_spec:
param_spec, sr = param_spec.split("s", 1)
sr = int(sr)
else:
sr = 1
if "c" in param_spec:
param_spec, kr = param_spec.split("c", 1)
kr = int(kr)
else:
kr = 1
mr, nr = map(int, param_spec.split("x"))
arch, isa = xnncommon.parse_target_name(target_name)
return mr, nr, kr, sr, arch, isa
def split_ukernel_name(name):
match = re.match(
r"^xnn_(f16|f32)_argmaxpool_ukernel_((\d+)p)?(\d+)x__(.+)_c(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
if match.group(2):
primary_tile = int(match.group(3))
incremental_tile = int(match.group(4))
else:
primary_tile = int(match.group(4))
incremental_tile = 0
channel_tile = int(match.group(6))
arch, isa = xnncommon.parse_target_name(target_name=match.group(5))
return primary_tile, incremental_tile, channel_tile, arch, isa
def split_ukernel_name(name):
match = re.match(
r"^xnn_(f16|f32)_dwconv2d_chw_ukernel_(\d+)x(\d+)(s2)?p(\d+)__(.+)_(\d+)x(\d+)(_acc\d+)?$",
name)
assert match is not None
kernel_height, kernel_width = int(match.group(2)), int(match.group(3))
if match.group(4):
assert match.group(4).startswith("s")
stride = int(match.group(4)[1:])
else:
stride = 1
padding = int(match.group(5))
height_tile = int(match.group(7))
width_tile = int(match.group(8))
arch, isa = xnncommon.parse_target_name(target_name=match.group(6))
return kernel_height, kernel_width, stride, padding, arch, isa, \
height_tile, width_tile
def split_ukernel_name(name):
match = re.match(
r"^xnn_(f16|f32)_(sigmoid|vabs|vneg|vsqr|vrndne|vrndz|vrndd|vrndu)_(fact_)?ukernel__(.+)_x(\d+)$",
name)
if match is None:
raise ValueError("Unexpected microkernel name: " + name)
op_type = {
"vabs": "Abs",
"vneg": "Negate",
"sigmoid": "Sigmoid",
"vrndne": "RoundToNearestEven",
"vrndz": "RoundTowardsZero",
"vrndu": "RoundUp",
"vrndd": "RoundDown",
"vsqr": "Square",
}[match.group(2)]
batch_tile = int(match.group(5))
arch, isa = xnncommon.parse_target_name(target_name=match.group(4))
return op_type, batch_tile, arch, isa
def split_ukernel_name(name):
common_name, target_name = name.split("__", 1)
common_parts = common_name.split("_")
param_spec = common_parts[-1]
assert param_spec.startswith("up")
if len(param_spec[2:].split("p")) > 1:
tile_part, kernel_part = param_spec[2:].split("p", 1)
primary_tile = int(tile_part)
cr, kr = map(int, kernel_part.split("x"))
else:
primary_tile = 0
cr, kr = map(int, param_spec[2:].split("x"))
arch, isa = xnncommon.parse_target_name(target_name)
requantization = common_parts[-3]
if requantization not in ["fp32", "rndnu"]:
requantization = None
return primary_tile, cr, kr, requantization, arch, isa
def split_ukernel_name(name):
common_name, target_name = name.split("__", 1)
common_parts = common_name.split("_")
xw = "gemm_xw_" in common_name
param_spec = common_parts[-1]
if "s" in param_spec:
param_spec, sr = param_spec.split("s", 1)
sr = int(sr)
else:
sr = 1
if "c" in param_spec:
param_spec, kr = param_spec.split("c", 1)
kr = int(kr)
else:
kr = 1
mr, nr = map(int, param_spec.split("x"))
arch, isa = xnncommon.parse_target_name(target_name)
requantization = common_parts[-3]
if requantization not in ["fp32", "rndnu"]:
requantization = None
return mr, nr, kr, sr, xw, requantization, arch, isa
