def copy_tb_files(self, sim_path):
if self.tb_file:
_tb_file = yTools.to_abs_list(self.tb_file, self.src_design)
else:
raw_tb_file = yTools.get_content_in_start_end(
self.do_template, re.compile("tb_start"), re.compile("tb_end"))
if not raw_tb_file:
yTools.say_it("Error. Not found raw tb files in %s" %
self.do_template)
return 1
_tb_file = list()
for item in raw_tb_file:
item_list = re.split("\s+", item)
pre_com = item_list[0].lower()
if pre_com in ("vlog", "vcom"):
_tb_file.append(item_list[-1])
if not _tb_file:
yTools.say_it("-Error. Not found tb files in %s" %
self.do_template)
return 1
_tb_file = yTools.to_abs_list(_tb_file,
os.path.dirname(self.do_template))
self.final_tb_files = list()
for item in _tb_file:
base_item = os.path.basename(item)
yTools.wrap_cp_file(item, os.path.join(sim_path, base_item))
self.final_tb_files.append(base_item)
def create_lct_file(self):
lct_file = self.kwargs.get("lct_file")
lct_template = os.path.join(self.conf, "classic", "lct.template")
if yTools.not_exists(lct_template, "LCT Template File"):
return 1
dst_lct_file = self.design + ".lct"
if self.devkit:
yTools.generate_file(dst_lct_file, lct_template, self.kwargs)
else:
src_lct_file = yTools.get_relative_path(lct_file, self.src_design)
if not os.path.isfile(src_lct_file):
src_lci_file = os.path.splitext(src_lct_file)[0] + ".lci"
if os.path.isfile(src_lci_file):
src_lct_file = src_lci_file
else:
for foo in os.listdir(self.src_design):
fext = os.path.splitext(foo.lower())[1]
if fext in (".lci", ".lct"):
src_lct_file = os.path.join(self.src_design, foo)
break
else:
yTools.say_it("Error. not found any lct file")
return 1
if yTools.wrap_cp_file(src_lct_file, dst_lct_file):
return 1
update_lct_file_if_necessary(dst_lct_file, self.goal)
if yTools.wrap_cp_file(dst_lct_file, self.design + ".lci"):
return 1
def start_from_syn(self, syn_file):
my_parser = xClassic.ProjectKwargs(syn_file, self.devkit)
my_parser.process()
self.kwargs = my_parser.get_prj_kwargs()
self.kwargs["lct_file"] = yTools.get_fname(syn_file) + ".lct"
yTools.say_it(self.kwargs, "original kwargs from syn file:",
self.debug)
def start_from_qas(self, qas_file):
if not self.devkit:
yTools.say_it("Message: use default devkit: %s" %
self.default_devkit)
self.devkit = self.default_devkit
self.kwargs["devkit"] = self.devkit
self.kwargs.update(xClassic.qas_kwargs(qas_file))
yTools.say_it(self.kwargs, "original kwargs from qas info file:",
self.debug)
def update_kwargs(self):
self.kwargs["date"] = time.strftime('%X')
self.kwargs["time"] = time.strftime('%x')
self.kwargs["synthesis_tool"] = self.synthesis
if self.goal == "Area":
self.kwargs["frequency"] = "1"
self.kwargs["global"] = "Nodes_collapsing_mode = Area;"
else:
self.kwargs["frequency"] = "200"
self.kwargs["global"] = ""
if self.check_module():
return 1
if self.check_devkit():
return 1
yTools.say_it(self.kwargs, "kwargs for classic command", self.debug)
def add_vlog_vcom_lines(self, src_files):
self.use_vhd = 0
v_v_lines = list()
for item in src_files:
fext = yTools.get_fext_lower(item)
item = yTools.win2unix(item, 0)
if fext in (".v", ".vo", ".sv"):
v_v_lines.append("vlog %s" % item)
elif fext in (".vho", ".vhd", ".vhdl"):
v_v_lines.append("vcom %s" % item)
if not self.use_vhd:
self.use_vhd = 1
elif fext == ".lpf":
continue
else:
yTools.say_it("-Warning. Unknown file: %s" % item)
continue
return v_v_lines
def get_original_kwargs(self):
self.has_syn_file = ""
qas_file = os.path.join(self.src_design, "_qas.info")
syn_files = yTools.find_by_fext(self.src_design, ".syn")
if not syn_files:
fit_dir = os.path.join(self.src_design, "fit")
if os.path.isdir(fit_dir):
syn_files = yTools.find_by_fext(fit_dir, ".syn")
len_syn = len(syn_files)
if os.path.isfile(qas_file):
return self.start_from_qas(qas_file)
elif len_syn == 1:
self.has_syn_file = syn_files[0]
return self.start_from_syn(syn_files[0])
else:
yTools.say_it("Error. Found %d Classic Project file in %s" %
(len_syn, self.src_design))
return 1
def run_check_only(self):
import glob
conf_file = glob.glob("*.conf")
if not conf_file:
return
self.qas = ""
report_path = self.run_options.get("cwd")
report = "check_flow.csv"
_job_dir, _design = os.path.split(os.path.dirname(self.job_design))
ta_check = check.TA(_job_dir,
_design,
report_path,
report,
self.qas,
self.tag,
rerun_path=report_path,
conf_file=self.run_options.get("check_conf"))
sts, text = ta_check.process()
yTools.say_it(text)
return sts
def check_module(self):
module = self.kwargs.get("module")
if not module:
yTools.say_it("Error. No source file specified")
return 1
final_module = list()
_base_dir = self.src_design
if self.has_syn_file:
_base_dir = os.path.dirname(self.has_syn_file)
for item in module:
new_item = yTools.get_relative_path(item, _base_dir)
fext = yTools.get_fext_lower(item)
if fext == ".lpf":
continue
if re.search("_tb\.", item):
self.kwargs["stimulus"] = [new_item]
continue
final_module.append(new_item)
self.kwargs["module"] = final_module
final_fext = [yTools.get_fext_lower(item) for item in final_module]
set_final_fext = set(final_fext)
final_fext_list = list(set_final_fext)
# Design Entry Type=ABEL/Schematic, Schematic/VHDL, Schematic/Verilog HDL, EDIF, Pure Verilog HDL, Pure VHDL
if ".abl" in final_fext_list:
entry_type = "ABEL/Schematic"
elif ".sch" in final_fext_list:
if ".vhd" in final_fext_list:
entry_type = "Schematic/VHDL"
elif ".v" in final_fext_list:
entry_type = "Schematic/Verilog HDL"
else:
entry_type = "ABEL/Schematic"
elif ".vhd" in final_fext_list:
entry_type = "Pure VHDL"
elif ".v" in final_fext_list:
entry_type = "Pure Verilog HDL"
else:
entry_type = "EDIF"
self.kwargs["source_format"] = self.entry_type = entry_type
self.kwargs["sds_source_format"] = re.sub("\s+", "_", entry_type)
def launch_pre_command_flow(self):
pre_kwargs = dict(install_dir=self.kwargs.get("install_dir"),
cpld_bin=self.kwargs.get("cpld_bin"),
design=self.kwargs.get("design"),
topmodule=self.kwargs.get("topmodule"))
pre_cmd_dict = self.cmd_dict.get("pre_command")
pre_log, pre_time = "pre_command.log", "pre_command.time"
if not pre_cmd_dict:
yTools.say_it(
"Error. Not any [pre_command] section in the command initial file"
)
return 1
# ------------------
template_dict = dict()
template_dict[".v"] = "vlog2jhd"
template_dict[".vhd"] = "vhd2jhd"
template_dict[".sch"] = "sch2jhd"
template_dict[".ed*"] = "edif2blf"
template_dict[".abl"] = "ahdl2blf"
for src in self.kwargs.get("module"):
if yTools.not_exists(src, "source file"):
return 1
fext = yTools.get_fext_lower(src)
fname = yTools.get_fname(src)
pre_kwargs["src"] = src
pre_kwargs["fname"] = fname
if fext.startswith(".ed"):
fext == ".ed*"
cmd_template = pre_cmd_dict.get(template_dict.get(fext, ""))
if not cmd_template:
continue
sts, cmd = yTools.get_cmd(cmd_template, pre_kwargs)
if sts:
return 1
if yTools.run_command(cmd, pre_log, pre_time):
return 1
def check_devkit(self):
"""
devkit comes from old ispLEVER project file
but the same devkit should be PartNumber in the lct file, otherwise the
"""
_devkit = self.kwargs.get("devkit")
if not _devkit:
yTools.say_it("Error. Not found devkit for Classic case")
return 1
section_ds = self.sds_dict.get("Device Support")
section_gd = self.sds_dict.get("Generic Devices")
#section_ot = self.sds_dict.get("Operating Temperature")
section_dev_sts = self.sds_dict.get("Device Status")
# LC4032B-10T44I=m4s_32_30,LC4032B,-10,44TQFP,IND,LSI4K-H32/30,lc4k32b,lc4k,P
# Format=DevFile,Device,Speed,Package,Condition,Info,VCIfile,DevKit,Status
devkit_lower = _devkit.lower()
devkit_lower = re.sub("ces$", "c", devkit_lower)
value = section_gd.get(devkit_lower)
value_title = section_ds.get("format")
self.kwargs["pkgname"] = section_ds.get("pkgname")
self.kwargs["devtargetlse"] = section_ds.get("devtargetlse")
self.kwargs["diename"] = section_ds.get("diename")
self.section_ds = section_ds
value_title = value_title.lower() # LOWER
if not value:
yTools.say_it("Error. Unknown Classic device: %s" % _devkit)
return 1
value_list = re.split("\s*,\s*", value.strip())
title_list = re.split("\s*,\s*", value_title.strip())
prefix = "sds_"
for i, item in enumerate(title_list):
key = prefix + item
value_item = value_list[i]
if item == "status":
self.kwargs[key] = section_dev_sts.get(value_item.lower())
else:
self.kwargs[key] = value_item
def get_file_list(section_case, src_design):
# say_it(section_case, "Section Case:")
_file_list = section_case.get("file list")
_file_list = re.split(",", _file_list)
_file_list = [item.strip() for item in _file_list]
file_list = list()
tb_file = ""
uut_name = ""
p_tb = re.compile("(\w+)_tb$", re.I)
for item in _file_list:
fname = yTools.get_fname(item)
fext = yTools.get_fext_lower(item)
item = yTools.win2unix(item, 0)
m_tb = p_tb.search(fname)
if m_tb:
tb_file = item
continue
if fext in (".v", ".vhd", ".sv"):
file_list.append(item)
else:
yTools.say_it("Warning. %s found in _qas.info" % item)
if tb_file:
new_tb_file = yTools.get_relative_path(tb_file, src_design)
if not os.path.isfile(new_tb_file):
yTools.say_it("-Error. Not found testbench file: %s" % tb_file)
else:
base_module_name = section_case.get("topmodule")
p_uut_name_verilog = re.compile("%s\s+(\w+)" % base_module_name)
# add_16_SIGNED post(
p_uut_name_vhdl = re.compile("(\S+)\s*:\s*%s" % base_module_name)
# uut: mac_ecp4_m5678_09x09_ir_or_dc_mclk_up PORT MAP(
fext = yTools.get_fext_lower(new_tb_file)
if fext == ".v":
matched_uut_name = yTools.simple_parser(new_tb_file, [p_uut_name_verilog,])
else:
matched_uut_name = yTools.simple_parser(new_tb_file, [p_uut_name_vhdl,])
if not matched_uut_name:
yTools.say_it("-Warning. can not find uut name in %s" % tb_file)
else:
uut_name = matched_uut_name[1].group(1)
return tb_file, file_list, uut_name