def is_byte_swap(self):
try:
self.model_variable()
except ModelIsConstrained:
return False
# Figure out if this might be a byte swap
byte_values_len = len(self.byte_values)
#print self.byte_values
if 1 < byte_values_len <= self.var.src.var.type.width:
var = create_BitVec(self.var.src, self.var.src.var.type.width)
ordering = list(reversed([
self.byte_values[x]
for x in sorted(self.byte_values.keys())
]))
reverse_var = Concat(
*reversed([
Extract(i-1, i-8, var)
for i in range(len(ordering) * 8, 0, -8)
])
)
if len(ordering) < 4:
reverse_var = Concat(
Extract(
31,
len(ordering)*8, var
),
reverse_var
)
reversed_ordering = reversed(ordering)
reversed_ordering = Concat(*reversed_ordering)
# The idea here is that if we add the negation of this, if it's
# not satisfiable, then that means there is no value such that
# the equivalence does not hold. If that is the case, then this
# should be a byte-swapped value.
self.solver.add(
Not(
And(
var == ZeroExt(
var.size() - len(ordering)*8,
Concat(*ordering)
),
reverse_var == ZeroExt(
reverse_var.size() - reversed_ordering.size(),
reversed_ordering
)
)
)
)
if self.solver.check() == unsat:
return True
return False
def right_one_extension(formula, bit_places):
"""Set the rest of bits on the right to 1.
"""
complement = BitVecVal(0, formula.size() - bit_places) - 1
formula = Concat(
Extract(formula.size() - 1,
formula.size() - bit_places, formula), complement)
return formula
def right_sign_extension(formula, bit_places):
"""Set the rest of bits on the right to the value of the sign bit.
"""
sign_bit_position = formula.size() - bit_places
sign_bit = Extract(sign_bit_position, sign_bit_position, formula)
complement = sign_bit
for _ in range(sign_bit_position - 1):
complement = Concat(sign_bit, complement)
formula = Concat(Extract(formula.size() - 1, sign_bit_position, formula),
complement)
return formula