def stack(clk, reset, enable, push_pop_stack, input_stack_1, output_stack_1, output_stack_2):
reg_1_out, reg_2_out, reg_3_out = [Signal(intbv(0)[32:]) for i in range(3)]
mux_1_out, mux_2_out, mux_3_out = [Signal(intbv(0)[32:]) for i in range(3)]
reg_1_out = output_stack_1
reg_2_out = output_stack_2
inside_clear = Signal(bool(0))
pp = push_pop_stack
mux_1 = mux2(a=input_stack_1, b=reg_2_out, sel=pp, result=mux_1_out)
reg_1 = registrador(clk=clk, input_1=mux_1_out, enable=enable, clear=inside_clear, output_1=reg_1_out)
mux_2 = mux2(a=reg_1_out, b=reg_3_out, sel=pp, result=mux_2_out)
reg_2 = registrador(clk=clk, input_1=mux_2_out, enable=enable, clear=inside_clear, output_1=reg_2_out)
mux_3 = mux2(a=reg_2_out, b=0, sel=pp, result=mux_3_out)
reg_3 = registrador(clk=clk, input_1=mux_3_out, enable=enable, clear=inside_clear, output_1=reg_3_out)
@always(clk.posedge)
def process1():
if reset:
inside_clear.next = 1
else:
inside_clear.next = 0
return process1, mux_1, reg_1, mux_2, reg_2, mux_3, reg_3
def addac(a, sel0, sel1, clk, acc):
invA = inv(a)
m1 = mux2(a, invA, sel0)
y1, cout = somador(a, acc, sel0)
m2 = mux2(m1, y1, sel1)
acc = flopenr(clk, 0, 1, m2, acc)
return m2, cout, acc
def test_case_mux2( self ):
"""Testando 1000 vezes o mux"""
def test( a, b, sel, result ):
for i in range( 10 ):
r_a, r_b = intbv( randrange( 32 ) )[32:], intbv( randrange( 32 ) )[32:]
a.next, b.next = r_a, r_b
sel.next = randrange( 2 )
yield delay( 1 )
if sel.val == 0:
expected = r_a
else:
expected = r_b
actual = result
self.assertEqual( actual, expected )
for width in range( 100 ):
a, b, result = [Signal( intbv( 0 )[32:] ) for i in range( 3 )]
sel = Signal( intbv( 0 )[1:] )
mux = mux2( a, b, sel, result )
check = test( a, b, sel, result )
sim = Simulation( mux, check )
sim.run( quiet=1 )
from mux2 import *
print("| d0 | d1 | s | y |")
for s in range(0, 2):
for d1 in range(0, 2, 1):
for d0 in range(0, 2, 1):
y = mux2(d0, d1, s)
print("| {0} | {1} | {2} | {3} |".format(d0, d1, s, y))
