def step(self):
if pipeline == 0:
RunSim_non_pipelined.RunSim_step(1, 1)
if pipeline == 1:
RunSim_stall.RunSim_step(1, 1)
if pipeline == 2:
RunSim_forward.RunSim_step(1, 1)
if pipeline == 0:
self.update_inst_cache(RunSim_non_pipelined.memory.text_module.
cache_module.cache_dict)
self.update_data_cache(RunSim_non_pipelined.memory.data_module.
cache_module.cache_dict)
if pipeline == 1:
self.update_inst_cache(
RunSim_stall.memory.text_module.cache_module.cache_dict)
self.update_data_cache(
RunSim_stall.memory.data_module.cache_module.cache_dict)
if pipeline == 2:
self.update_inst_cache(
RunSim_forward.memory.text_module.cache_module.cache_dict)
self.update_data_cache(
RunSim_forward.memory.data_module.cache_module.cache_dict)
with open(f"RegisterDump.mc", "w") as fileReg:
for i in range(32): # for all 32 registers
fileReg.write(f"x{i} ") # print address of register for eg. x5
if (RunSim_forward.registers.reg[i] >= 0):
fileReg.write(
self.padhexa(hex(
RunSim_forward.registers.reg[i])).upper().replace(
'X', 'x'))
else:
reg = RunSim_forward.registers.reg[i] & 0xffffffff # signed
fileReg.write(hex(reg).upper().replace('X', 'x'))
fileReg.write("\n")
#dumping memory
with open(
f"MemoryDump.mc", "w"
) as fileMem: # input is dictionary with key as address and value as data
lst = [] # stores keys present in dictionary
temp_lst = [] # stores base address
for key in RunSim_forward.memory.data_module.memory:
lst.append(key)
lst.sort()
for x in lst:
temp = x - (x % 4) # storing base address in temp
if temp not in temp_lst: # if base address not present in temp_list , then append it
temp_lst.append(temp)
temp_lst.sort()
for i in temp_lst:
fileMem.write(
f"{(self.padhexa(hex(i)).upper().replace('X', 'x'))} "
) # printing base address
if i in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.data_module.memory[i])).upper())[8:]} "
) # if key in dictionary, print its data
else:
fileMem.write("00 ") # if key not in dictionary, print 00
if (i + 1) in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.data_module.memory[i + 1])).upper())[8:]} "
)
else:
fileMem.write("00 ")
if (i + 2) in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.data_module.memory[i + 2])).upper())[8:]} "
)
else:
fileMem.write("00 ")
if (i + 3) in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.data_module.memory[i + 3])).upper())[8:]} "
)
else:
fileMem.write("00 ")
fileMem.write("\n") # new line
lst = [] # stores keys present in dictionary
temp_lst = []
for key in RunSim_forward.memory.text_module.memory:
lst.append(key)
lst.sort()
for x in lst:
temp = x - (x % 4) # storing base address in temp
if temp not in temp_lst: # if base address not present in temp_list , then append it
temp_lst.append(temp)
temp_lst.sort()
for i in temp_lst:
fileMem.write(
f"{(self.padhexa(hex(i)).upper().replace('X', 'x'))} "
) # printing base address
if i in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.text_module.memory[i])).upper())[8:]} "
) # if key in dictionary, print its data
else:
fileMem.write("00 ") # if key not in dictionary, print 00
if (i + 1) in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.text_module.memory[i + 1])).upper())[8:]} "
)
else:
fileMem.write("00 ")
if (i + 2) in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.text_module.memory[i + 2])).upper())[8:]} "
)
else:
fileMem.write("00 ")
if (i + 3) in lst:
fileMem.write(
f"{(self.padhexa(hex(RunSim_forward.memory.text_module.memory[i + 3])).upper())[8:]} "
)
else:
fileMem.write("00 ")
fileMem.write("\n") # new line
def step(self):
global error
if error:
return
reg_list = []
mem_dict = {}
stats = None
if pipeline == 0:
stats = RunSim_non_pipelined.RunSim_step(1, 1)
mem_dict = {
**RunSim_non_pipelined.memory.text_module.memory,
**RunSim_non_pipelined.memory.data_module.memory
} #RunSim_non_pipelined.memory.text_module.update(RunSim_non_pipelined.memory.data_module)
self.update_memory(mem_dict)
self.update_inst_cache(
RunSim_non_pipelined.memory.text_module.cache_module.
cache_dict,
RunSim_non_pipelined.memory.text_module.cache_block_size)
self.update_data_cache(
RunSim_non_pipelined.memory.data_module.cache_module.
cache_dict,
RunSim_non_pipelined.memory.data_module.cache_block_size)
reg_list = RunSim_non_pipelined.registers.reg
self.update_registers(reg_list)
self.Icache_stats.setPlainText(
f"Total Accesses: {RunSim_non_pipelined.memory.text_module.cache_accesses}\n\nTotal Hits: {RunSim_non_pipelined.memory.text_module.cache_hits}\n\nTotal Miss: {RunSim_non_pipelined.memory.text_module.cache_miss}"
)
self.Dcache_stats.setPlainText(
f"Total Accesses: {RunSim_non_pipelined.memory.data_module.cache_accesses}\n\nTotal Hits: {RunSim_non_pipelined.memory.data_module.cache_hits}\n\nTotal Miss: {RunSim_non_pipelined.memory.data_module.cache_miss}"
)
self.clock_display.display(RunSim_non_pipelined.clock)
if pipeline == 1:
stats = RunSim_stall.RunSim_step(1, 1)
mem_dict = {
**RunSim_stall.memory.text_module.memory,
**RunSim_stall.memory.data_module.memory
}
self.update_memory(mem_dict)
self.update_inst_cache(
RunSim_stall.memory.text_module.cache_module.cache_dict,
RunSim_stall.memory.text_module.cache_block_size)
self.update_data_cache(
RunSim_stall.memory.data_module.cache_module.cache_dict,
RunSim_stall.memory.data_module.cache_block_size)
reg_list = RunSim_stall.registers.reg
self.update_registers(reg_list)
self.Icache_stats.setPlainText(
f"Total Accesses: {RunSim_stall.memory.text_module.cache_accesses}\n\nTotal Hits: {RunSim_stall.memory.text_module.cache_hits}\n\nTotal Miss: {RunSim_stall.memory.text_module.cache_miss}"
)
self.Dcache_stats.setPlainText(
f"Total Accesses: {RunSim_stall.memory.data_module.cache_accesses}\n\nTotal Hits: {RunSim_stall.memory.data_module.cache_hits}\n\nTotal Miss: {RunSim_stall.memory.data_module.cache_miss}"
)
self.clock_display.display(RunSim_stall.clock)
if pipeline == 2:
stats = RunSim_forward.RunSim_step(1, 1)
mem_dict = {
**RunSim_forward.memory.text_module.memory,
**RunSim_forward.memory.data_module.memory
}
self.update_memory(mem_dict)
self.update_inst_cache(
RunSim_forward.memory.text_module.cache_module.cache_dict,
RunSim_forward.memory.text_module.cache_block_size)
self.update_data_cache(
RunSim_forward.memory.data_module.cache_module.cache_dict,
RunSim_forward.memory.data_module.cache_block_size)
reg_list = RunSim_forward.registers.reg
self.update_registers(reg_list)
self.Icache_stats.setPlainText(
f"Total Accesses: {RunSim_forward.memory.text_module.cache_accesses}\n\nTotal Hits: {RunSim_forward.memory.text_module.cache_hits}\n\nTotal Miss: {RunSim_forward.memory.text_module.cache_miss}"
)
self.Dcache_stats.setPlainText(
f"Total Accesses: {RunSim_forward.memory.data_module.cache_accesses}\n\nTotal Hits: {RunSim_forward.memory.data_module.cache_hits}\n\nTotal Miss: {RunSim_forward.memory.data_module.cache_miss}"
)
self.clock_display.display(RunSim_forward.clock)
with open(f"RegisterDump.mc", "w") as fileReg:
for i in range(32): # for all 32 registers
fileReg.write(f"x{i} ") # print address of register for eg. x5
if (reg_list[i] >= 0):
fileReg.write(
self.padhexa(hex(reg_list[i])).upper().replace(
'X', 'x'))
else:
reg = reg_list[i] & 0xffffffff # signed
fileReg.write(hex(reg).upper().replace('X', 'x'))
fileReg.write("\n")
#dumping memory
with open(
f"MemoryDump.mc", "w"
) as fileMem: # input is dictionary with key as address and value as data
lst = [] # stores keys present in dictionary
temp_lst = [] # stores base mem_dict:
for key in mem_dict:
lst.append(key)
lst.sort()
for x in lst:
temp = x - (x % 4) # storing base address in temp
if temp not in temp_lst: # if base address not present in temp_list , then append it
temp_lst.append(temp)
temp_lst.sort()
for i in temp_lst:
fileMem.write(
f"{(self.padhexa(hex(i)).upper().replace('X', 'x'))} "
) # printing base address
if i in lst:
fileMem.write(
f"{(self.padhexa(hex(mem_dict[i])).upper())[8:]} "
) # if key in dictionary, print its data
else:
fileMem.write("00 ") # if key not in dictionary, print 00
if (i + 1) in lst:
fileMem.write(
f"{(self.padhexa(hex(mem_dict[i + 1])).upper())[8:]} ")
else:
fileMem.write("00 ")
if (i + 2) in lst:
fileMem.write(
f"{(self.padhexa(hex(mem_dict[i + 2])).upper())[8:]} ")
else:
fileMem.write("00 ")
if (i + 3) in lst:
fileMem.write(
f"{(self.padhexa(hex(mem_dict[i + 3])).upper())[8:]} ")
else:
fileMem.write("00 ")
fileMem.write("\n") # new line
if stats == "NPE": # for non pipelined ending
self.console.setPlainText("Program Terminated Successfully!")
elif stats != None:
self.console.setPlainText("Program Terminated Successfully!")
self.console.appendPlainText("Stats-")
self.console.appendPlainText(f"Stat1: Cycles: {stats[0]}")
self.console.appendPlainText(
f"Stat2: Total Instructions: {stats[1]}")
self.console.appendPlainText(f"Stat3: CPI: {stats[2]}")
self.console.appendPlainText(f"Stat4: Load/Store: {stats[3]}")
self.console.appendPlainText(
f"Stat5: ALU instructions: {stats[4]}")
self.console.appendPlainText(
f"Stat6: Control instructions: {stats[5]}")
self.console.appendPlainText(f"Stat7: Bubbles: {stats[6]}")
self.console.appendPlainText(
f"Stat8: Total Data Hazards: {stats[7]}")
self.console.appendPlainText(
f"Stat9: Total Control Hazards: {stats[8]}")
self.console.appendPlainText(
f"Stat10: Total branch mispredictions: {stats[9]}")
self.console.appendPlainText(
f"Stat11: Stalls due to data hazard: {stats[10]}")
self.console.appendPlainText(
f"Stat12: Stalls due to control hazard: {stats[11]}")
self.console.verticalScrollBar().setValue(0)
print(
"\033[1;92mRegister and memory outputs written in RegisterDump.mc and MemoryDump.mc respectively\033[0m"
)
else:
self.console.setPlainText("Executing....")
# !/usr/bin/python3
import MachineCodeParser # import parser for parsing machine code into PC and corresponding instructions.
import RunSim_non_pipelined
import sys
#import memory
if(len(sys.argv)==1):
print("File name not supplied!")
sys.exit()
MachineCodeParser.parser(sys.argv[1]) # supply input file name
#program load
RunSim_non_pipelined.memory.InitMemory(MachineCodeParser.PC_INST, MachineCodeParser.DATA)
#Run the simulator
RunSim_non_pipelined.RunSim()
####################################################file dumping############################################################
# this fxn extends 0x2 to 0x00000002
def padhexa(s):
return '0x' + s[2:].zfill(8)
#def print_reg(arr): # input is numpy array
with open(f"RegisterDump_non_pipelined.mc", "w") as fileReg:
for i in range(32): # for all 32 registers
fileReg.write(f"x{i} ") # print address of register for eg. x5
if (RunSim_non_pipelined.registers.reg[i] >= 0):
fileReg.write(padhexa(hex(RunSim_non_pipelined.registers.reg[i])).upper().replace('X', 'x'))
else:
reg = RunSim_non_pipelined.registers.reg[i] & 0xffffffff # signed