class BasicRom: storage: any output_wire: BusWire size: int input_wire: BusWire def __init__(self, length: int): self.size = length self.storage = [None for x in range(length)] self.output_wire = BusWire() self.input_wire = BusWire() def add_instruction(self, pos: int, instruction: any): if pos > self.size or pos < 0: return -1 self.storage[pos] = instruction return 1 def read_instruction(self): if self.input_wire.get_data() > self.size or self.input_wire.get_data( ) < 0: return -1 self.output_wire.set_data(self.storage[self.input_wire.get_data()]) return 1 def notify(self): self.read_instruction()
def __init__(self): self.input_data = BusWire() self.input_driver = BusWire() self.output = BusWire() self.and_gate = AndGate() self.and_gate.input.append(self.input_data) self.and_gate.input.append(self.input_driver) self.output.set_input(self.and_gate.output)
def __init__(self, pages: int, rows: int): self.storage = [[None for x in range(rows)] for y in range(pages)] self.pages = pages self.rows = rows self.input = BusWire() self.address = BusWire() self.opcode = BusWire() self.output = BusWire()
class Clock: rate: int notifyList: list = [] output: BusWire = BusWire() stop: int def __init__(self, rate: int): self.rate = rate self.output.set_data(0) self.stop = 0 def run(self): self.output.set_data(not self.output.get_data()) #print(self.output.get_data()) for elem in self.notifyList: elem.notify() time.sleep(1 / self.rate) if self.stop == 0: self.run() def add_notify(self, object: any): self.notifyList.append(object) def stop_programm(self): self.stop = 1
class ThreeWireDriver: input_a: BusWire input_b: BusWire input_c: BusWire output: BusWire input_driver_a: BusWire input_driver_b: BusWire input_driver_c: BusWire and_gate_one_to_or: BusWire and_gate_two_to_or: BusWire and_gate_three_to_or: BusWire and_gate_one: AndGate and_gate_two: AndGate and_gate_three: AndGate or_gate: OrGate def __init__(self): self.input_a = BusWire() self.input_b = BusWire() self.input_c = BusWire() self.and_gate_one_to_or = BusWire() self.and_gate_two_to_or = BusWire() self.and_gate_three_to_or = BusWire() self.input_driver_a = BusWire() self.input_driver_b = BusWire() self.input_driver_c = BusWire() self.output = BusWire() self.and_gate_one = AndGate() self.and_gate_two = AndGate() self.and_gate_three = AndGate() self.or_gate = OrGate() self.and_gate_one.input.append(self.input_a) self.and_gate_one.input.append(self.input_driver_a) self.and_gate_one_to_or.set_input(self.and_gate_one.output) self.and_gate_two.input.append(self.input_b) self.and_gate_two.input.append(self.input_driver_b) self.and_gate_two_to_or.set_input(self.and_gate_two.output) self.and_gate_three.input.append(self.input_c) self.and_gate_three.input.append(self.input_driver_c) self.and_gate_three_to_or.set_input(self.and_gate_three.output) self.or_gate.input.append(self.and_gate_one_to_or) self.or_gate.input.append(self.and_gate_two_to_or) self.or_gate.input.append(self.and_gate_three_to_or) self.output.set_input(self.or_gate.output) def notify(self): self.and_gate_one.notify() self.and_gate_two.notify() self.and_gate_three.notify() self.or_gate.notify()
class AddingUnit: input_a: BusWire input_b: BusWire output: BusWire def __init__(self): self.input_a = BusWire() self.input_b = BusWire() self.output = BusWire() def add(self): result = int(self.input_a.get_data(), 2) + int(self.input_b.get_data(), 2) out = bin(result)[2:].zfill(8) self.output.set_data(out) def notify(self): self.add()
class SingleWireDriver: input_data: BusWire input_driver: BusWire output: BusWire and_gate: AndGate def __init__(self): self.input_data = BusWire() self.input_driver = BusWire() self.output = BusWire() self.and_gate = AndGate() self.and_gate.input.append(self.input_data) self.and_gate.input.append(self.input_driver) self.output.set_input(self.and_gate.output) def notify(self): self.and_gate.notify()
class InstructionCounter: input = BusWire() count = -1 output = BusWire() currentinput: any = 0 data_input = BusWire() op_input = BusWire() def notify(self): if self.currentinput is not self.input.get_data(): self.currentinput = self.input.get_data() if int(self.op_input.get_data(), 2) == 1: self.count = int(self.data_input.get_data(), 2) else: self.count += 1 self.output.set_data(self.count) #print("ic_out") #print(self.output.get_data())
class ConsoleOut: input: BusWire input_op: BusWire def __init__(self): self.input = BusWire() self.input_op = BusWire() def out(self): if self.input_op.get_data() == "1": character = self.input.get_data()[:1] data = self.input.get_data()[1:] if character == "1": print(chr(int(data, 2))) if character == "0": print(int(data, 2)) def notify(self): self.out()
class NotGate: input: BusWire output: BusWire def __init__(self): self.input = BusWire() self.output = BusWire() # Bitwise and gate for n number of inputs def calculate(self): ##inputs = list(inputs) ##output: any = self.input.get_data() bit_len = 8 mask = int("11111111", 2) ##inputs.pop(0) output = ~int(self.input.get_data(), 2) & mask self.output.set_data(bin(output)[2:].zfill(8)) ##self.output.set_data(output) return bin(output)[2:].zfill(8) def notify(self): self.calculate()
class AndGate: input: [] output: BusWire def __init__(self): self.input = [] self.output = BusWire() # Bitwise and gate for n number of inputs def calculate(self): ##inputs = list(inputs) output: any = int(self.input[0].get_data(), 2) bit_len = output.bit_length() ##inputs.pop(0) for value in self.input: output &= int(value.get_data(), 2) self.output.set_data(bin(output)[2:].zfill(8)) return bin(output)[2:].zfill(8) def notify(self): self.calculate()
class BasicRam: pages: int rows: int storage: any input: BusWire output: BusWire opcode: BusWire address: BusWire def __init__(self, pages: int, rows: int): self.storage = [[None for x in range(rows)] for y in range(pages)] self.pages = pages self.rows = rows self.input = BusWire() self.address = BusWire() self.opcode = BusWire() self.output = BusWire() def store(self): store_address = int(self.address.get_data(), 2) page = store_address // 8 row = store_address % 8 if self.storage[page][row] is None: self.storage[page][row] = self.input.get_data() return (page, row) print("RamOverload") return (-1, -1) def read(self): store_address = int(self.address.get_data(), 2) page = store_address // 8 row = store_address % 8 self.output.set_data(self.storage[page][row]) return self.storage[page][row] def delete(self): store_address = int(self.address.get_data(), 2) page = store_address // 8 row = store_address % 8 self.storage[page][row] = None def notify(self): op = self.opcode.get_data() if op == "10": self.store() if op == "11": self.read()
def __init__(self): self.input = BusWire() self.input_op = BusWire() self.output_a = BusWire() self.output_b = BusWire() self.not_to_and = BusWire() self.and_gate_one = AndGate() self.and_gate_two = AndGate() self.not_gate = NotGate() self.not_gate.input.set_input(self.input_op) self.not_to_and.set_input(self.not_gate.output) self.and_gate_one.input.append(self.input) self.and_gate_one.input.append(self.input_op) self.and_gate_two.input.append(self.input) self.and_gate_two.input.append(self.not_to_and) self.output_a.set_input(self.and_gate_one.output) self.output_b.set_input(self.and_gate_two.output)
class TwoWireDemultiplexer: input: BusWire input_op: BusWire output_a: BusWire output_b: BusWire not_to_and: BusWire and_gate_one: AndGate and_gate_two: AndGate not_gate: NotGate def __init__(self): self.input = BusWire() self.input_op = BusWire() self.output_a = BusWire() self.output_b = BusWire() self.not_to_and = BusWire() self.and_gate_one = AndGate() self.and_gate_two = AndGate() self.not_gate = NotGate() self.not_gate.input.set_input(self.input_op) self.not_to_and.set_input(self.not_gate.output) self.and_gate_one.input.append(self.input) self.and_gate_one.input.append(self.input_op) self.and_gate_two.input.append(self.input) self.and_gate_two.input.append(self.not_to_and) self.output_a.set_input(self.and_gate_one.output) self.output_b.set_input(self.and_gate_two.output) def notify(self): self.not_gate.notify() self.and_gate_one.notify() self.and_gate_two.notify()
def __init__(self): self.input_a = BusWire() self.input_b = BusWire() self.input_c = BusWire() self.and_gate_one_to_or = BusWire() self.and_gate_two_to_or = BusWire() self.and_gate_three_to_or = BusWire() self.input_driver_a = BusWire() self.input_driver_b = BusWire() self.input_driver_c = BusWire() self.output = BusWire() self.and_gate_one = AndGate() self.and_gate_two = AndGate() self.and_gate_three = AndGate() self.or_gate = OrGate() self.and_gate_one.input.append(self.input_a) self.and_gate_one.input.append(self.input_driver_a) self.and_gate_one_to_or.set_input(self.and_gate_one.output) self.and_gate_two.input.append(self.input_b) self.and_gate_two.input.append(self.input_driver_b) self.and_gate_two_to_or.set_input(self.and_gate_two.output) self.and_gate_three.input.append(self.input_c) self.and_gate_three.input.append(self.input_driver_c) self.and_gate_three_to_or.set_input(self.and_gate_three.output) self.or_gate.input.append(self.and_gate_one_to_or) self.or_gate.input.append(self.and_gate_two_to_or) self.or_gate.input.append(self.and_gate_three_to_or) self.output.set_input(self.or_gate.output)
class FourWireMultiplexer: input_a: BusWire input_b: BusWire input_c: BusWire input_d: BusWire output: BusWire op_a: BusWire op_b: BusWire not_a_one_to_and: BusWire not_a_tow_to_and: BusWire not_b_one_to_and: BusWire not_c_two_to_and: BusWire and_one_to_or: BusWire and_two_to_or: BusWire and_three_to_or: BusWire and_four_to_or: BusWire and_gate_one: AndGate not_gate_one: NotGate not_gate_two: NotGate and_gate_two: AndGate not_gate_three: NotGate and_gate_three: AndGate not_gate_four: NotGate and_gate_four: AndGate or_gate: OrGate def __init__(self): self.input_a = BusWire() self.input_b = BusWire() self.input_c = BusWire() self.input_d = BusWire() self.output = BusWire() self.op_a = BusWire() self.op_b = BusWire() self.not_a_one_to_and = BusWire() self.not_a_tow_to_and = BusWire() self.not_b_one_to_and = BusWire() self.not_c_two_to_and = BusWire() self.and_one_to_or = BusWire() self.and_two_to_or = BusWire() self.and_three_to_or = BusWire() self.and_four_to_or = BusWire() self.and_gate_one = AndGate() self.not_gate_one = NotGate() self.not_gate_two = NotGate() self.and_gate_two = AndGate() self.not_gate_three = NotGate() self.and_gate_three = AndGate() self.not_gate_four = NotGate() self.and_gate_four = AndGate() self.or_gate = OrGate() ##For and_gate_one self.not_gate_one.input.set_input(self.op_a) self.not_gate_three.input.set_input(self.op_a) self.not_gate_two.input.set_input(self.op_b) self.not_a_one_to_and.set_input(self.not_gate_one.output) self.not_a_tow_to_and.set_input(self.not_gate_two.output) self.and_gate_one.input.append(self.input_a) self.and_gate_one.input.append(self.not_a_one_to_and) self.and_gate_one.input.append(self.not_a_tow_to_and) self.and_one_to_or.set_input(self.and_gate_one.output) ##For and_gate_two self.not_b_one_to_and.set_input(self.not_gate_three.output) self.and_gate_two.input.append(self.not_b_one_to_and) self.and_gate_two.input.append(self.input_b) self.and_gate_two.input.append(self.op_b) self.and_two_to_or.set_input(self.and_gate_two.output) ##For and_gate_three self.not_gate_four.input.set_input(self.op_b) self.not_c_two_to_and.set_input(self.not_gate_four.output) self.and_gate_three.input.append(self.op_a) self.and_gate_three.input.append(self.input_c) self.and_gate_three.input.append(self.not_c_two_to_and) self.and_three_to_or.set_input(self.and_gate_three.output) ##For and_gate_four self.and_gate_four.input.append(self.input_d) self.and_gate_four.input.append(self.op_b) self.and_four_to_or.set_input(self.and_gate_four.output) self.and_gate_four.input.append(self.op_a) ##For or_gate self.or_gate.input.append(self.and_one_to_or) self.or_gate.input.append(self.and_two_to_or) self.or_gate.input.append(self.and_three_to_or) self.or_gate.input.append(self.and_four_to_or) self.output.set_input(self.or_gate.output) def set_data(self): self.not_gate_one.notify() self.not_gate_two.notify() self.not_gate_three.notify() self.not_gate_four.notify() self.and_gate_one.notify() self.and_gate_two.notify() self.and_gate_three.notify() self.and_gate_four.notify() self.or_gate.notify() def notify(self): self.set_data()
def __init__(self): self.input_a = BusWire() self.input_b = BusWire() self.input_c = BusWire() self.input_d = BusWire() self.output = BusWire() self.op_a = BusWire() self.op_b = BusWire() self.not_a_one_to_and = BusWire() self.not_a_tow_to_and = BusWire() self.not_b_one_to_and = BusWire() self.not_c_two_to_and = BusWire() self.and_one_to_or = BusWire() self.and_two_to_or = BusWire() self.and_three_to_or = BusWire() self.and_four_to_or = BusWire() self.and_gate_one = AndGate() self.not_gate_one = NotGate() self.not_gate_two = NotGate() self.and_gate_two = AndGate() self.not_gate_three = NotGate() self.and_gate_three = AndGate() self.not_gate_four = NotGate() self.and_gate_four = AndGate() self.or_gate = OrGate() ##For and_gate_one self.not_gate_one.input.set_input(self.op_a) self.not_gate_three.input.set_input(self.op_a) self.not_gate_two.input.set_input(self.op_b) self.not_a_one_to_and.set_input(self.not_gate_one.output) self.not_a_tow_to_and.set_input(self.not_gate_two.output) self.and_gate_one.input.append(self.input_a) self.and_gate_one.input.append(self.not_a_one_to_and) self.and_gate_one.input.append(self.not_a_tow_to_and) self.and_one_to_or.set_input(self.and_gate_one.output) ##For and_gate_two self.not_b_one_to_and.set_input(self.not_gate_three.output) self.and_gate_two.input.append(self.not_b_one_to_and) self.and_gate_two.input.append(self.input_b) self.and_gate_two.input.append(self.op_b) self.and_two_to_or.set_input(self.and_gate_two.output) ##For and_gate_three self.not_gate_four.input.set_input(self.op_b) self.not_c_two_to_and.set_input(self.not_gate_four.output) self.and_gate_three.input.append(self.op_a) self.and_gate_three.input.append(self.input_c) self.and_gate_three.input.append(self.not_c_two_to_and) self.and_three_to_or.set_input(self.and_gate_three.output) ##For and_gate_four self.and_gate_four.input.append(self.input_d) self.and_gate_four.input.append(self.op_b) self.and_four_to_or.set_input(self.and_gate_four.output) self.and_gate_four.input.append(self.op_a) ##For or_gate self.or_gate.input.append(self.and_one_to_or) self.or_gate.input.append(self.and_two_to_or) self.or_gate.input.append(self.and_three_to_or) self.or_gate.input.append(self.and_four_to_or) self.output.set_input(self.or_gate.output)
def __init__(self): self.input = [] self.output = BusWire()
class ControlUnit: input_wire: BusWire ic_out_op: BusWire ic_out_data: BusWire reg_demux_op_a: BusWire reg_demux_op_b: BusWire reg_op: BusWire reg_mux_op_a: BusWire reg_mux_op_b: BusWire reg_to_adding_driver_out_op: BusWire reg_to_adding_ram_demux_out_o: BusWire cout_out_op: BusWire addi_out_data: BusWire ram_out_adress: BusWire ram_out_op: BusWire ldi_out_data: BusWire adding_ldi_ram_driver_out_op_a: BusWire adding_ldi_ram_driver_out_op_b: BusWire adding_ldi_ram_driver_out_op_c: BusWire four_wire_multiplexer: FourWireMultiplexer four_wire_demultiplexer: FourWireDemultiplexer console_out: ConsoleOut single_wire_driver: SingleWireDriver three_wire_driver: ThreeWireDriver two_wire_demultiplexer: TwoWireDemultiplexer ram: BasicRam adding_unit: AddingUnit register: Register opcode: str reg_one: str reg_two: str data: any clock: Clock def __init__(self): self.input_wire = BusWire() self.ic_out_op = BusWire() self.ic_out_data = BusWire() self.reg_demux_op_a = BusWire() self.reg_demux_op_b = BusWire() self.reg_op = BusWire() self.reg_mux_op_a = BusWire() self.reg_mux_op_b = BusWire() self.reg_to_adding_driver_out_op = BusWire() self.reg_to_adding_ram_demux_out_o = BusWire() self.cout_out_op = BusWire() self.addi_out_data = BusWire() self.ram_out_adress = BusWire() self.ram_out_op = BusWire() self.ldi_out_data = BusWire() self.adding_ldi_ram_driver_out_op_a = BusWire() self.adding_ldi_ram_driver_out_op_b = BusWire() self.adding_ldi_ram_driver_out_op_c = BusWire() self.four_wire_multiplexer = None self.four_wire_demultiplexer = None self.register = None self.two_wire_demultiplexer = None self.ram = None self.adding_unit = None self.single_wire_driver = None self.three_wire_driver = None self.console_out = None self.clock = None self.opcode = "" self.reg_one = "" self.reg_two = "" self.data = "" def set_outputs(self): self.resetOuts() self.data = self.input_wire.get_data() #print("this is data") #print(self.input_wire.get_data()) if self.data is not None: self.opcode = self.data[:3] self.reg_one = self.data[3:][:2] self.reg_two = self.data[5:][:2] charakter_bit = self.data[7:][:1] self.data = self.data[8:][:8] self.choose_instruction() def notify(self): self.set_outputs() def resetOuts(self): self.ic_out_op.set_data("00000000") self.ic_out_data.set_data("00000000") self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("00000000") self.reg_op.set_data("00000000") self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("00000000") self.reg_to_adding_driver_out_op.set_data("00000000") self.reg_to_adding_ram_demux_out_o.set_data("00000000") self.cout_out_op.set_data("00000000") self.addi_out_data.set_data("00000000") self.ram_out_adress.set_data("00000000") self.ram_out_op.set_data("00000000") self.ldi_out_data.set_data("00000000") self.adding_ldi_ram_driver_out_op_a.set_data("00000000") self.adding_ldi_ram_driver_out_op_b.set_data("00000000") self.adding_ldi_ram_driver_out_op_c.set_data("00000000") def choose_instruction(self): if self.opcode == "001": self.load_from_ram() if self.opcode == "010": self.load_immidiate() if self.opcode == "011": self.add_immidiate() if self.opcode == "100": self.store() if self.opcode == "101": self.console_print() if self.opcode == "000": self.register_copy() if self.opcode == "111": self.exit_programm() def load_immidiate(self): self.resetOuts() self.ldi_out_data.set_data(self.data) self.adding_ldi_ram_driver_out_op_a.set_data("11111111") self.adding_ldi_ram_driver_out_op_b.set_data("00000000") self.adding_ldi_ram_driver_out_op_c.set_data("00000000") choosen_reg = int(self.reg_one, 2) if choosen_reg == 0: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("11111111") self.reg_op.set_data("001") if choosen_reg == 1: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("11111111") self.reg_op.set_data("010") if choosen_reg == 2: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("00000000") self.reg_op.set_data("011") if choosen_reg == 3: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("00000000") self.reg_op.set_data("100") self.three_wire_driver.notify() self.four_wire_demultiplexer.notify() self.register.notify() def add_immidiate(self): self.resetOuts() self.adding_ldi_ram_driver_out_op_a.set_data("00000000") self.adding_ldi_ram_driver_out_op_b.set_data("11111111") self.adding_ldi_ram_driver_out_op_c.set_data("00000000") self.addi_out_data.set_data(self.data) self.reg_to_adding_driver_out_op.set_data("11111111") choosen_reg = int(self.reg_one, 2) if choosen_reg == 0: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("11111111") self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("00000000") self.reg_op.set_data("001") if choosen_reg == 1: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("11111111") self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("11111111") self.reg_op.set_data("010") if choosen_reg == 2: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("00000000") self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("00000000") self.reg_op.set_data("011") if choosen_reg == 3: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("00000000") self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("11111111") self.reg_op.set_data("100") self.reg_to_adding_ram_demux_out_o.set_data("11111111") self.four_wire_multiplexer.notify() self.single_wire_driver.notify() self.two_wire_demultiplexer.notify() self.adding_unit.notify() self.three_wire_driver.notify() self.four_wire_demultiplexer.notify() self.register.notify() def store(self): self.resetOuts() self.reg_to_adding_driver_out_op.set_data("11111111") self.reg_to_adding_ram_demux_out_o.set_data("00000000") choosen_reg = int(self.reg_one, 2) if choosen_reg == 0: self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("00000000") if choosen_reg == 1: self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("11111111") if choosen_reg == 2: self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("00000000") if choosen_reg == 3: self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("11111111") self.ram_out_adress.set_data(self.data) self.ram_out_op.set_data("10") self.four_wire_multiplexer.notify() self.single_wire_driver.notify() self.two_wire_demultiplexer.notify() self.ram.notify() def console_print(self): self.resetOuts() self.reg_to_adding_driver_out_op.set_data("11111111") self.reg_to_adding_ram_demux_out_o.set_data("00000000") choosen_reg = int(self.reg_one, 2) if choosen_reg == 0: self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("00000000") if choosen_reg == 1: self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("11111111") if choosen_reg == 2: self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("00000000") if choosen_reg == 3: self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("11111111") self.cout_out_op.set_data("1") self.four_wire_multiplexer.notify() self.single_wire_driver.notify() self.two_wire_demultiplexer.notify() self.console_out.notify() def load_from_ram(self): self.resetOuts() self.ldi_out_data.set_data(self.data) self.adding_ldi_ram_driver_out_op_a.set_data("00000000") self.adding_ldi_ram_driver_out_op_b.set_data("00000000") self.adding_ldi_ram_driver_out_op_c.set_data("11111111") choosen_reg = int(self.reg_one, 2) if choosen_reg == 0: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("11111111") self.reg_op.set_data("001") if choosen_reg == 1: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("11111111") self.reg_op.set_data("010") if choosen_reg == 2: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("00000000") self.reg_op.set_data("011") if choosen_reg == 3: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("00000000") self.reg_op.set_data("100") self.ram_out_adress.set_data(self.data) self.ram_out_op.set_data("11") self.ram.notify() self.three_wire_driver.notify() self.four_wire_demultiplexer.notify() self.register.notify() def register_copy(self): self.resetOuts() self.adding_ldi_ram_driver_out_op_a.set_data("00000000") self.adding_ldi_ram_driver_out_op_b.set_data("11111111") self.adding_ldi_ram_driver_out_op_c.set_data("00000000") self.addi_out_data.set_data("00000000") self.reg_to_adding_driver_out_op.set_data("11111111") choosen_reg_dest = int(self.reg_one, 2) choosen_reg_src = int(self.reg_two, 2) if choosen_reg_src == 0: self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("00000000") if choosen_reg_src == 1: self.reg_mux_op_a.set_data("00000000") self.reg_mux_op_b.set_data("11111111") if choosen_reg_src == 2: self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("00000000") if choosen_reg_src == 3: self.reg_mux_op_a.set_data("11111111") self.reg_mux_op_b.set_data("11111111") if choosen_reg_dest == 0: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("11111111") self.reg_op.set_data("001") if choosen_reg_dest == 1: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("11111111") self.reg_op.set_data("010") if choosen_reg_dest == 2: self.reg_demux_op_a.set_data("11111111") self.reg_demux_op_b.set_data("00000000") self.reg_op.set_data("011") if choosen_reg_dest == 3: self.reg_demux_op_a.set_data("00000000") self.reg_demux_op_b.set_data("00000000") self.reg_op.set_data("100") self.reg_to_adding_ram_demux_out_o.set_data("11111111") self.four_wire_multiplexer.notify() self.single_wire_driver.notify() self.two_wire_demultiplexer.notify() self.adding_unit.notify() self.three_wire_driver.notify() self.four_wire_demultiplexer.notify() self.register.notify() def exit_programm(self): self.clock.stop_programm()
def __init__(self): self.input_wire = BusWire() self.ic_out_op = BusWire() self.ic_out_data = BusWire() self.reg_demux_op_a = BusWire() self.reg_demux_op_b = BusWire() self.reg_op = BusWire() self.reg_mux_op_a = BusWire() self.reg_mux_op_b = BusWire() self.reg_to_adding_driver_out_op = BusWire() self.reg_to_adding_ram_demux_out_o = BusWire() self.cout_out_op = BusWire() self.addi_out_data = BusWire() self.ram_out_adress = BusWire() self.ram_out_op = BusWire() self.ldi_out_data = BusWire() self.adding_ldi_ram_driver_out_op_a = BusWire() self.adding_ldi_ram_driver_out_op_b = BusWire() self.adding_ldi_ram_driver_out_op_c = BusWire() self.four_wire_multiplexer = None self.four_wire_demultiplexer = None self.register = None self.two_wire_demultiplexer = None self.ram = None self.adding_unit = None self.single_wire_driver = None self.three_wire_driver = None self.console_out = None self.clock = None self.opcode = "" self.reg_one = "" self.reg_two = "" self.data = ""
def __init__(self): self.input_a = BusWire() self.input_b = BusWire() self.output = BusWire()
def __init__(self): self.counter = 0 self.clock = Clock(10) self.instruction_counter = InstructionCounter() self.rom = BasicRom(64) self.control_unit = ControlUnit() self.ram = BasicRam(8, 8) self.adding_unit = AddingUnit() self.register = Register() self.reg_multiplexer = FourWireMultiplexer() self.reg_demultiplexer = FourWireDemultiplexer() self.console_out = ConsoleOut() self.adding_ram_demux = TwoWireDemultiplexer() self.reg_to_ram_adding_driver = SingleWireDriver() self.adding_ldi_ram_to_data_driver = ThreeWireDriver() self.clock_to_ic = BusWire() self.ic_to_rom = BusWire() self.rom_to_cu = BusWire() self.cu_to_ic_data = BusWire() self.cu_to_ic_op = BusWire() self.cu_to_reg_demux_op_a = BusWire() self.cu_to_reg_demux_op_b = BusWire() self.cu_to_reg_op = BusWire() self.cu_to_reg_mux_op_a = BusWire() self.cu_to_reg_mux_op_b = BusWire() self.cu_to_adding_ram_driver_op = BusWire() self.cu_to_adding_ram_demux = BusWire() self.cu_to_cout_op = BusWire() self.cu_to_ram_adress = BusWire() self.cu_to_ram_op = BusWire() self.cu_to_adding_ldi_ram_driver_in_a = BusWire() self.cu_to_adding_ldi_ram_driver_op_a = BusWire() self.cu_to_adding_ldi_ram_driver_op_b = BusWire() self.cu_to_adding_ldi_ram_driver_op_c = BusWire() self.cu_to_adding_data = BusWire() self.adding_ldi_ram_to_reg_demux = BusWire() self.reg_demux_out_a_to_reg_a = BusWire() self.reg_demux_out_b_to_reg_b = BusWire() self.reg_demux_out_c_to_reg_c = BusWire() self.reg_demux_out_d_to_reg_d = BusWire() self.reg_out_a_to_reg_mux_in_a = BusWire() self.reg_out_b_to_reg_mux_in_b = BusWire() self.reg_out_c_to_reg_mux_in_c = BusWire() self.reg_out_d_to_reg_mux_in_d = BusWire() self.reg_mux_out_to_adding_ram_driver = BusWire() self.adding_ram_driver_to_adding_ram_demux_in = BusWire() self.adding_ram_demux_out_a_to_adding = BusWire() self.adding_ram_demux_out_b_to_ram = BusWire() self.adding_to_adding_ldi_ram_driver_in_b = BusWire() self.ram_to_adding_ldi_ram_in_c = BusWire() self.clock_to_ic.set_input(self.clock.output) self.instruction_counter.input.set_input(self.clock_to_ic) self.ic_to_rom.set_input(self.instruction_counter.output) self.rom.input_wire.set_input(self.ic_to_rom) self.rom_to_cu.set_input(self.rom.output_wire) self.control_unit.input_wire.set_input(self.rom_to_cu) self.cu_to_ic_op.set_input(self.control_unit.ic_out_op) self.instruction_counter.op_input.set_input(self.cu_to_ic_op) self.cu_to_ic_data.set_input(self.control_unit.ic_out_data) self.instruction_counter.data_input.set_input(self.cu_to_ic_data) # self.cu_to_reg_demux_op_a.set_input(self.control_unit.reg_demux_op_a) self.reg_demultiplexer.input_op_one.set_input(self.cu_to_reg_demux_op_a) self.cu_to_reg_demux_op_b.set_input(self.control_unit.reg_demux_op_b) self.reg_demultiplexer.input_op_two.set_input(self.cu_to_reg_demux_op_b) self.cu_to_reg_mux_op_a.set_input(self.control_unit.reg_mux_op_a) self.reg_multiplexer.op_a.set_input(self.cu_to_reg_mux_op_a) self.cu_to_reg_mux_op_b.set_input(self.control_unit.reg_mux_op_b) self.reg_multiplexer.op_b.set_input(self.cu_to_reg_mux_op_b) self.reg_demux_out_a_to_reg_a.set_input(self.reg_demultiplexer.output_a) self.register.input_a.set_input(self.reg_demux_out_a_to_reg_a) self.reg_demux_out_b_to_reg_b.set_input(self.reg_demultiplexer.output_b) self.register.input_b.set_input(self.reg_demux_out_b_to_reg_b) self.reg_demux_out_c_to_reg_c.set_input(self.reg_demultiplexer.output_c) self.register.input_c.set_input(self.reg_demux_out_c_to_reg_c) self.reg_demux_out_d_to_reg_d.set_input(self.reg_demultiplexer.output_d) self.register.input_d.set_input(self.reg_demux_out_d_to_reg_d) self.cu_to_reg_op.set_input(self.control_unit.reg_op) self.register.input_op.set_input(self.cu_to_reg_op) self.reg_out_a_to_reg_mux_in_a.set_input(self.register.out_a) self.reg_multiplexer.input_a.set_input(self.reg_out_a_to_reg_mux_in_a) self.reg_out_b_to_reg_mux_in_b.set_input(self.register.out_b) self.reg_multiplexer.input_b.set_input(self.reg_out_b_to_reg_mux_in_b) self.reg_out_c_to_reg_mux_in_c.set_input(self.register.out_c) self.reg_multiplexer.input_c.set_input(self.reg_out_c_to_reg_mux_in_c) self.reg_out_d_to_reg_mux_in_d.set_input(self.register.out_d) self.reg_multiplexer.input_d.set_input(self.reg_out_d_to_reg_mux_in_d) self.reg_mux_out_to_adding_ram_driver.set_input(self.reg_multiplexer.output) self.reg_to_ram_adding_driver.input_data.set_input(self.reg_mux_out_to_adding_ram_driver) self.cu_to_adding_ram_driver_op.set_input(self.control_unit.reg_to_adding_driver_out_op) self.reg_to_ram_adding_driver.input_driver.set_input(self.cu_to_adding_ram_driver_op) self.adding_ram_driver_to_adding_ram_demux_in.set_input(self.reg_to_ram_adding_driver.output) self.adding_ram_demux.input.set_input(self.adding_ram_driver_to_adding_ram_demux_in) self.cu_to_adding_ram_demux.set_input(self.control_unit.reg_to_adding_ram_demux_out_o) self.adding_ram_demux.input_op.set_input(self.cu_to_adding_ram_demux) self.adding_ram_demux_out_a_to_adding.set_input(self.adding_ram_demux.output_a) self.adding_unit.input_a.set_input(self.adding_ram_demux_out_a_to_adding) self.cu_to_adding_data.set_input(self.control_unit.addi_out_data) self.adding_unit.input_b.set_input(self.cu_to_adding_data) self.adding_ram_demux_out_b_to_ram.set_input(self.adding_ram_demux.output_b) self.ram.input.set_input(self.adding_ram_demux_out_b_to_ram) self.console_out.input.set_input(self.adding_ram_demux_out_b_to_ram) self.cu_to_cout_op.set_input(self.control_unit.cout_out_op) self.console_out.input_op.set_input(self.cu_to_cout_op) self.cu_to_ram_op.set_input(self.control_unit.ram_out_op) self.ram.opcode.set_input(self.cu_to_ram_op) self.cu_to_ram_adress.set_input(self.control_unit.ram_out_adress) self.ram.address.set_input(self.cu_to_ram_adress) self.cu_to_adding_ldi_ram_driver_in_a.set_input(self.control_unit.ldi_out_data) self.adding_ldi_ram_to_data_driver.input_a.set_input(self.cu_to_adding_ldi_ram_driver_in_a) self.adding_to_adding_ldi_ram_driver_in_b.set_input(self.adding_unit.output) self.adding_ldi_ram_to_data_driver.input_b.set_input(self.adding_to_adding_ldi_ram_driver_in_b) self.ram_to_adding_ldi_ram_in_c.set_input(self.ram.output) self.adding_ldi_ram_to_data_driver.input_c.set_input(self.ram_to_adding_ldi_ram_in_c) self.cu_to_adding_ldi_ram_driver_op_a.set_input(self.control_unit.adding_ldi_ram_driver_out_op_a) self.adding_ldi_ram_to_data_driver.input_driver_a.set_input(self.cu_to_adding_ldi_ram_driver_op_a) self.cu_to_adding_ldi_ram_driver_op_b.set_input(self.control_unit.adding_ldi_ram_driver_out_op_b) self.adding_ldi_ram_to_data_driver.input_driver_b.set_input(self.cu_to_adding_ldi_ram_driver_op_b) self.cu_to_adding_ldi_ram_driver_op_c.set_input(self.control_unit.adding_ldi_ram_driver_out_op_c) self.adding_ldi_ram_to_data_driver.input_driver_c.set_input(self.cu_to_adding_ldi_ram_driver_op_c) self.adding_ldi_ram_to_reg_demux.set_input(self.adding_ldi_ram_to_data_driver.output) self.reg_demultiplexer.input.set_input(self.adding_ldi_ram_to_reg_demux) self.control_unit.three_wire_driver = self.adding_ldi_ram_to_data_driver self.control_unit.single_wire_driver = self.reg_to_ram_adding_driver self.control_unit.register = self.register self.control_unit.four_wire_demultiplexer = self.reg_demultiplexer self.control_unit.four_wire_multiplexer = self.reg_multiplexer self.control_unit.two_wire_demultiplexer = self.adding_ram_demux self.control_unit.ram = self.ram self.control_unit.console_out = self.console_out self.control_unit.adding_unit = self.adding_unit self.control_unit.clock = self.clock
class ProcessorSystem: clock: Clock instruction_counter: InstructionCounter rom: BasicRom control_unit: ControlUnit ram: BasicRam adding_unit: AddingUnit register: Register reg_multiplexer: FourWireMultiplexer reg_demultiplexer: FourWireDemultiplexer console_out: ConsoleOut adding_ram_demux: TwoWireDemultiplexer reg_to_ram_adding_driver: SingleWireDriver adding_ldi_ram_to_data_driver: ThreeWireDriver clock_to_ic: BusWire ic_to_rom: BusWire rom_to_cu: BusWire cu_to_ic_data: BusWire cu_to_ic_op: BusWire cu_to_reg_demux_op_a: BusWire cu_to_reg_demux_op_b: BusWire cu_to_reg_op: BusWire cu_to_reg_mux_op_a: BusWire cu_to_reg_mux_op_b: BusWire cu_to_adding_ram_driver_op: BusWire cu_to_adding_ram_demux: BusWire cu_to_cout_op: BusWire cu_to_ram_adress: BusWire cu_to_ram_op: BusWire cu_to_adding_ldi_ram_driver_in_a: BusWire cu_to_adding_ldi_ram_driver_op_a: BusWire cu_to_adding_ldi_ram_driver_op_b: BusWire cu_to_adding_ldi_ram_driver_op_c: BusWire cu_to_adding_data: BusWire adding_ldi_ram_to_reg_demux: BusWire reg_demux_out_a_to_reg_a: BusWire reg_demux_out_b_to_reg_b: BusWire reg_demux_out_c_to_reg_c: BusWire reg_demux_out_d_to_reg_d: BusWire reg_out_a_to_reg_mux_in_a: BusWire reg_out_b_to_reg_mux_in_b: BusWire reg_out_c_to_reg_mux_in_c: BusWire reg_out_d_to_reg_mux_in_d: BusWire reg_mux_out_to_adding_ram_driver: BusWire adding_ram_driver_to_adding_ram_demux_in: BusWire adding_ram_demux_out_a_to_adding: BusWire adding_ram_demux_out_b_to_ram: BusWire adding_to_adding_ldi_ram_driver_in_b: BusWire ram_to_adding_ldi_ram_in_c: BusWire counter: int def __init__(self): self.counter = 0 self.clock = Clock(10) self.instruction_counter = InstructionCounter() self.rom = BasicRom(64) self.control_unit = ControlUnit() self.ram = BasicRam(8, 8) self.adding_unit = AddingUnit() self.register = Register() self.reg_multiplexer = FourWireMultiplexer() self.reg_demultiplexer = FourWireDemultiplexer() self.console_out = ConsoleOut() self.adding_ram_demux = TwoWireDemultiplexer() self.reg_to_ram_adding_driver = SingleWireDriver() self.adding_ldi_ram_to_data_driver = ThreeWireDriver() self.clock_to_ic = BusWire() self.ic_to_rom = BusWire() self.rom_to_cu = BusWire() self.cu_to_ic_data = BusWire() self.cu_to_ic_op = BusWire() self.cu_to_reg_demux_op_a = BusWire() self.cu_to_reg_demux_op_b = BusWire() self.cu_to_reg_op = BusWire() self.cu_to_reg_mux_op_a = BusWire() self.cu_to_reg_mux_op_b = BusWire() self.cu_to_adding_ram_driver_op = BusWire() self.cu_to_adding_ram_demux = BusWire() self.cu_to_cout_op = BusWire() self.cu_to_ram_adress = BusWire() self.cu_to_ram_op = BusWire() self.cu_to_adding_ldi_ram_driver_in_a = BusWire() self.cu_to_adding_ldi_ram_driver_op_a = BusWire() self.cu_to_adding_ldi_ram_driver_op_b = BusWire() self.cu_to_adding_ldi_ram_driver_op_c = BusWire() self.cu_to_adding_data = BusWire() self.adding_ldi_ram_to_reg_demux = BusWire() self.reg_demux_out_a_to_reg_a = BusWire() self.reg_demux_out_b_to_reg_b = BusWire() self.reg_demux_out_c_to_reg_c = BusWire() self.reg_demux_out_d_to_reg_d = BusWire() self.reg_out_a_to_reg_mux_in_a = BusWire() self.reg_out_b_to_reg_mux_in_b = BusWire() self.reg_out_c_to_reg_mux_in_c = BusWire() self.reg_out_d_to_reg_mux_in_d = BusWire() self.reg_mux_out_to_adding_ram_driver = BusWire() self.adding_ram_driver_to_adding_ram_demux_in = BusWire() self.adding_ram_demux_out_a_to_adding = BusWire() self.adding_ram_demux_out_b_to_ram = BusWire() self.adding_to_adding_ldi_ram_driver_in_b = BusWire() self.ram_to_adding_ldi_ram_in_c = BusWire() self.clock_to_ic.set_input(self.clock.output) self.instruction_counter.input.set_input(self.clock_to_ic) self.ic_to_rom.set_input(self.instruction_counter.output) self.rom.input_wire.set_input(self.ic_to_rom) self.rom_to_cu.set_input(self.rom.output_wire) self.control_unit.input_wire.set_input(self.rom_to_cu) self.cu_to_ic_op.set_input(self.control_unit.ic_out_op) self.instruction_counter.op_input.set_input(self.cu_to_ic_op) self.cu_to_ic_data.set_input(self.control_unit.ic_out_data) self.instruction_counter.data_input.set_input(self.cu_to_ic_data) # self.cu_to_reg_demux_op_a.set_input(self.control_unit.reg_demux_op_a) self.reg_demultiplexer.input_op_one.set_input(self.cu_to_reg_demux_op_a) self.cu_to_reg_demux_op_b.set_input(self.control_unit.reg_demux_op_b) self.reg_demultiplexer.input_op_two.set_input(self.cu_to_reg_demux_op_b) self.cu_to_reg_mux_op_a.set_input(self.control_unit.reg_mux_op_a) self.reg_multiplexer.op_a.set_input(self.cu_to_reg_mux_op_a) self.cu_to_reg_mux_op_b.set_input(self.control_unit.reg_mux_op_b) self.reg_multiplexer.op_b.set_input(self.cu_to_reg_mux_op_b) self.reg_demux_out_a_to_reg_a.set_input(self.reg_demultiplexer.output_a) self.register.input_a.set_input(self.reg_demux_out_a_to_reg_a) self.reg_demux_out_b_to_reg_b.set_input(self.reg_demultiplexer.output_b) self.register.input_b.set_input(self.reg_demux_out_b_to_reg_b) self.reg_demux_out_c_to_reg_c.set_input(self.reg_demultiplexer.output_c) self.register.input_c.set_input(self.reg_demux_out_c_to_reg_c) self.reg_demux_out_d_to_reg_d.set_input(self.reg_demultiplexer.output_d) self.register.input_d.set_input(self.reg_demux_out_d_to_reg_d) self.cu_to_reg_op.set_input(self.control_unit.reg_op) self.register.input_op.set_input(self.cu_to_reg_op) self.reg_out_a_to_reg_mux_in_a.set_input(self.register.out_a) self.reg_multiplexer.input_a.set_input(self.reg_out_a_to_reg_mux_in_a) self.reg_out_b_to_reg_mux_in_b.set_input(self.register.out_b) self.reg_multiplexer.input_b.set_input(self.reg_out_b_to_reg_mux_in_b) self.reg_out_c_to_reg_mux_in_c.set_input(self.register.out_c) self.reg_multiplexer.input_c.set_input(self.reg_out_c_to_reg_mux_in_c) self.reg_out_d_to_reg_mux_in_d.set_input(self.register.out_d) self.reg_multiplexer.input_d.set_input(self.reg_out_d_to_reg_mux_in_d) self.reg_mux_out_to_adding_ram_driver.set_input(self.reg_multiplexer.output) self.reg_to_ram_adding_driver.input_data.set_input(self.reg_mux_out_to_adding_ram_driver) self.cu_to_adding_ram_driver_op.set_input(self.control_unit.reg_to_adding_driver_out_op) self.reg_to_ram_adding_driver.input_driver.set_input(self.cu_to_adding_ram_driver_op) self.adding_ram_driver_to_adding_ram_demux_in.set_input(self.reg_to_ram_adding_driver.output) self.adding_ram_demux.input.set_input(self.adding_ram_driver_to_adding_ram_demux_in) self.cu_to_adding_ram_demux.set_input(self.control_unit.reg_to_adding_ram_demux_out_o) self.adding_ram_demux.input_op.set_input(self.cu_to_adding_ram_demux) self.adding_ram_demux_out_a_to_adding.set_input(self.adding_ram_demux.output_a) self.adding_unit.input_a.set_input(self.adding_ram_demux_out_a_to_adding) self.cu_to_adding_data.set_input(self.control_unit.addi_out_data) self.adding_unit.input_b.set_input(self.cu_to_adding_data) self.adding_ram_demux_out_b_to_ram.set_input(self.adding_ram_demux.output_b) self.ram.input.set_input(self.adding_ram_demux_out_b_to_ram) self.console_out.input.set_input(self.adding_ram_demux_out_b_to_ram) self.cu_to_cout_op.set_input(self.control_unit.cout_out_op) self.console_out.input_op.set_input(self.cu_to_cout_op) self.cu_to_ram_op.set_input(self.control_unit.ram_out_op) self.ram.opcode.set_input(self.cu_to_ram_op) self.cu_to_ram_adress.set_input(self.control_unit.ram_out_adress) self.ram.address.set_input(self.cu_to_ram_adress) self.cu_to_adding_ldi_ram_driver_in_a.set_input(self.control_unit.ldi_out_data) self.adding_ldi_ram_to_data_driver.input_a.set_input(self.cu_to_adding_ldi_ram_driver_in_a) self.adding_to_adding_ldi_ram_driver_in_b.set_input(self.adding_unit.output) self.adding_ldi_ram_to_data_driver.input_b.set_input(self.adding_to_adding_ldi_ram_driver_in_b) self.ram_to_adding_ldi_ram_in_c.set_input(self.ram.output) self.adding_ldi_ram_to_data_driver.input_c.set_input(self.ram_to_adding_ldi_ram_in_c) self.cu_to_adding_ldi_ram_driver_op_a.set_input(self.control_unit.adding_ldi_ram_driver_out_op_a) self.adding_ldi_ram_to_data_driver.input_driver_a.set_input(self.cu_to_adding_ldi_ram_driver_op_a) self.cu_to_adding_ldi_ram_driver_op_b.set_input(self.control_unit.adding_ldi_ram_driver_out_op_b) self.adding_ldi_ram_to_data_driver.input_driver_b.set_input(self.cu_to_adding_ldi_ram_driver_op_b) self.cu_to_adding_ldi_ram_driver_op_c.set_input(self.control_unit.adding_ldi_ram_driver_out_op_c) self.adding_ldi_ram_to_data_driver.input_driver_c.set_input(self.cu_to_adding_ldi_ram_driver_op_c) self.adding_ldi_ram_to_reg_demux.set_input(self.adding_ldi_ram_to_data_driver.output) self.reg_demultiplexer.input.set_input(self.adding_ldi_ram_to_reg_demux) self.control_unit.three_wire_driver = self.adding_ldi_ram_to_data_driver self.control_unit.single_wire_driver = self.reg_to_ram_adding_driver self.control_unit.register = self.register self.control_unit.four_wire_demultiplexer = self.reg_demultiplexer self.control_unit.four_wire_multiplexer = self.reg_multiplexer self.control_unit.two_wire_demultiplexer = self.adding_ram_demux self.control_unit.ram = self.ram self.control_unit.console_out = self.console_out self.control_unit.adding_unit = self.adding_unit self.control_unit.clock = self.clock def flashcommand(self, command: str): self.rom.add_instruction(self.counter, command) self.counter += 1 def run(self): self.clock.add_notify(self.instruction_counter) self.clock.add_notify(self.rom) self.clock.add_notify(self.control_unit) self.clock.run()
def __init__(self, length: int): self.size = length self.storage = [None for x in range(length)] self.output_wire = BusWire() self.input_wire = BusWire()
def __init__(self): self.input = BusWire() self.input_op = BusWire()