def __init__(self, fun: ir.Fun, bbl: ir.Bbl, allow_spilling,
gpr_available_lac: int, gpr_available_not_lac: int, flt_available_lac: int,
flt_available_not_lac: int):
super(CpuRegPool, self).__init__()
self._fun = fun
self._bbl = bbl
self._allow_spilling = allow_spilling
# set of registers that are ready to be allocated subject to the
# reserved regions below. Should use an ordered set here?
# Note, the int is a bit-mask
self._gpr_available_lac: int = gpr_available_lac
self._gpr_available_not_lac: int = gpr_available_not_lac
# for FLT and DBL since the register are overlapping
self._flt_available_lac: int = flt_available_lac
self._flt_available_not_lac: int = flt_available_not_lac
self._gpr_reserved: List[reg_alloc.PreAllocation] = [
reg_alloc.PreAllocation() for _ in range(len(_GPR_REGS))]
self._flt_reserved: List[reg_alloc.PreAllocation] = [
reg_alloc.PreAllocation() for _ in range(len(_FLT_REGS))]
def __init__(self, regs: List[ir.CpuReg]):
self.available: Dict[int, List[ir.CpuReg]] = {
GPR_NOT_LAC: [],
GPR_LAC: [],
FLT_NOT_LAC: [],
FLT_LAC: [],
}
self.set_available: Set[ir.CpuReg] = set()
self.reserved: Dict[ir.CpuReg, reg_alloc.PreAllocation] = {}
for cpu_reg in regs:
self.reserved[cpu_reg] = reg_alloc.PreAllocation()
heapq.heappush(self.available[cpu_reg.kind], cpu_reg)
self.set_available.add(cpu_reg)