Ejemplo n.º 1
0
    def testMov(self):
        mov = o.Opcode.Lookup("mov")
        ins = ir.Ins(mov, [reg_u32, reg_u32])
        sanity.InsCheckConstraints(ins)

        with self.assertRaises(sanity.ParseError):
            ins = ir.Ins(mov, [reg_s32, reg_u32])
            sanity.InsCheckConstraints(ins)

        with self.assertRaises(sanity.ParseError):
            ins = ir.Ins(mov, [reg_s32, reg_s8])
            sanity.InsCheckConstraints(ins)
Ejemplo n.º 2
0
def ProcessLine(token: List, unit: ir.Unit, fun: Optional[ir.Fun],
                cpu_regs: Dict[str, ir.Reg]):
    opc = o.Opcode.Table.get(token[0])
    if not opc:
        raise ir.ParseError(f"unknown opcode/directive: {token}")
    if opc == o.LEA:
        if token[2] in unit.fun_syms:
            opc = o.LEA_FUN
        elif token[2] in unit.mem_syms:
            opc = o.LEA_MEM
        elif token[2] in fun.stk_syms:
            opc = o.LEA_STK

        if opc != o.LEA_FUN and len(token) < 4:
            token.append("0")
    if len(token) - 1 != len(opc.operand_kinds):
        raise ir.ParseError("operand number %d mismatch: %s" %
                            (len(opc.operand_kinds), token))

    if token[0].startswith("."):
        operands = RetrieveActualOperands(unit, fun, opc, token, {})
        directive = DIR_DISPATCHER[token[0]]
        directive(unit, operands)

    else:
        assert fun is not None
        operands = RetrieveActualOperands(unit, fun, opc, token, cpu_regs)
        assert fun.bbls, f"no bbl specified to contain instruction"
        bbl = fun.bbls[-1]
        ins = ir.Ins(opc, operands)
        bbl.AddIns(ins)
        sanity.InsCheckConstraints(ins)
Ejemplo n.º 3
0
def ProcessLine(token: List, unit: ir.Unit, fun: Optional[ir.Fun],
                cpu_regs: Dict[str, ir.Reg]):
    opc = o.Opcode.Table.get(token[0])
    if not opc:
        raise ir.ParseError(f"unknown opcode/directive: {token}")
    # TODO: get rid of this hack which simplifies FrontEndC/translate.py a bit
    if opc == o.LEA:
        if token[2] in fun.reg_syms:
            pass  # in case the register name is shadows a global
        elif token[2] in unit.fun_syms:
            opc = o.LEA_FUN
        elif token[2] in unit.mem_syms:
            opc = o.LEA_MEM
        elif token[2] in fun.stk_syms:
            opc = o.LEA_STK

        if opc != o.LEA_FUN and len(token) < 4:
            token.append("0")
    if len(token) - 1 != len(opc.operand_kinds):
        raise ir.ParseError(
            f"operand number {len(opc.operand_kinds)} mismatch: {token}")

    if token[0].startswith("."):
        operands = RetrieveActualOperands(unit, fun, opc, token, {})
        directive = DIR_DISPATCHER[token[0]]
        directive(unit, operands)

    else:
        assert fun is not None
        operands = RetrieveActualOperands(unit, fun, opc, token, cpu_regs)
        assert fun.bbls, f"no bbl specified to contain instruction"
        bbl = fun.bbls[-1]
        ins = ir.Ins(opc, operands)
        bbl.AddIns(ins)
        sanity.InsCheckConstraints(ins)
Ejemplo n.º 4
0
    def testAdd2(self):
        ld = o.Opcode.Lookup("ld")
        ins = ir.Ins(ld, [reg_u32, reg_a32, reg_u32])
        sanity.InsCheckConstraints(ins)

        ins = ir.Ins(ld, [reg_u32, reg_a32, reg_u16])
        sanity.InsCheckConstraints(ins)

        ins = ir.Ins(ld, [reg_u32, reg_a32, reg_s32])
        sanity.InsCheckConstraints(ins)

        with self.assertRaises(sanity.ParseError):
            ins = ir.Ins(ld, [reg_u32, reg_u32, reg_u32])
            sanity.InsCheckConstraints(ins)

        with self.assertRaises(sanity.ParseError):
            ins = ir.Ins(ld, [reg_u32, reg_a32, reg_a32])
            sanity.InsCheckConstraints(ins)