def test_basic(dump_vcd):
# Elaborate the model
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool(model)
sim.reset()
print ""
# Helper function
def t(in_, out):
# Write input value to input port
model.in_.value = in_
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# If reference output is not '?', verify value read from output port
if (out != '?'):
assert model.out == out
# Tick simulator one cycle
sim.cycle()
# ''' TUTORIAL TASK ''''''''''''''''''''''''''''''''''''''''''''''''''''
# This test script is incomplete. As part of the tutorial you will
# insert a sequence of test cases that use the above helper function to
# set the input and verify the output of the registered incrementer.
# ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
# Cycle-by-cycle tests
t(0x00, '?')
t(0x13, 0x01)
t(0x27, 0x14)
t(0x00, 0x28)
t(0x00, 0x01)
t(0x00, 0x01)
def test_basic( dump_vcd ):
# Elaborate the model
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool( model )
sim.reset()
print ""
# Helper function
def t( in_, out ):
# Write input value to input port
model.in_.value = in_
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# If reference output is not '?', verify value read from output port
if ( out != '?' ):
assert model.out == out
# Tick simulator one cycle
sim.cycle()
# ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''''''
# This test script is incomplete. As part of the tutorial you will add
# a sequence of test cases to set the input and verify the output of
# the registered incrementer.
# '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''
# Cylce-by-cycle tests
t(0x00, '?')
t(0x13, 0x01)
t(0x27, 0x14)
t(0x00, 0x28)
t(0x00, 0x01)
t(0x00, 0x01)
def test_basic( dump_vcd = None):
# Elaborate the model
model = RegIncr()
v = TranslationTool(model)
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool( model )
sim.reset()
print ""
# Helper function
def t( in_, out ):
# Write input value to input port
model.in_.value = in_
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# If reference output is not '?', verify value read from output port
if ( out != '?' ):
assert model.out == out
# Tick simulator one cycle
sim.cycle()
# Cycle-by-cycle tests
t( 0x00, '?' )
t( 0x13, 0x01 )
t( 0x27, 0x14 )
t( 0x00, 0x28 )
t( 0x00, 0x01 )
t( 0x00, 0x01 )
def test_basic( dump_vcd ):
# Elaborate the model
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
# Create and reset simulator
sim = SimulationTool( model )
sim.reset()
print ""
# Helper function
def t( in_, out ):
# Write input value to input port
model.in_.value = in_
# Ensure that all combinational concurrent blocks are called
sim.eval_combinational()
# Display a line trace
sim.print_line_trace()
# If reference output is not '?', verify value read from output port
if ( out != '?' ):
assert model.out == out
# Tick simulator one cycle
sim.cycle()
# Cycle-by-cycle tests
t( 0x00, '?' )
t( 0x13, 0x01 )
t( 0x27, 0x14 )
t( 0x00, 0x28 )
t( 0x00, 0x01 )
t( 0x00, 0x01 )
def test_basic(dump_vcd):
model = RegIncr()
model.vcd_file = dump_vcd
model.elaborate()
sim = SimulationTool(model)
sim.reset()
def t(in_, out):
model.in_.value = in_
sim.eval_combinational()
sim.print_line_trace()
if out != '?':
assert model.out == out
sim.cycle()
t(0x00, '?')
t(0x13, 0x01)
t(0x27, 0x14)
t(0x00, 0x28)
t(0x00, 0x01)
t(0x00, 0x01)
from sys import argv
from RegIncr import RegIncr
# Get list of input values from command line
input_values = [int(x, 0) for x in argv[1:]]
# Add three zero values to end of list of input values
input_values.extend([0] * 3)
# Elaborate the model
model = RegIncr()
model.vcd_file = "regincr-sim.vcd"
model.elaborate()
# Create a simulator using simulation tool
sim = SimulationTool(model)
# Reset simulator
sim.reset()
# Apply input values and display output values
for input_value in input_values:
# Write input value to input port
#!/usr/bin/python
# -*- coding:utf-8 -*-
from pymtl import *
from sys import argv
from RegIncr import RegIncr
input_values = [int(x, 0) for x in argv[1:]]
input_values.extend([0] * 3)
model = RegIncr()
model.vcd_file = "regincr-sim.vcd"
model.elaborate()
sim = SimulationTool(model)
sim.reset()
for input_value in input_values:
# Write input value to input port
model.in_.value = input_value
# Display input and output ports
sim.print_line_trace()
# Tick simulator one cycle
sim.cycle()
