def main():
MDO = MDOCommand
UO_ = UOCommand
ChD = ReadCommand
ZR_ = WriteCommand
scheduler = Scheduler(ALU, FPU, BUS, DMA)
scheduler.add(
MDO(1, ALU, cached=0),
UO_(2, FPU, cached=0),
UO_(1, ALU, cached=1),
MDO(1, FPU, cached=0),
MDO(1, FPU, cached=0),
UO_(1, ALU, cached=0),
MDO(2, ALU, cached=1),
UO_(1, FPU, cached=1),
UO_(2, ALU, cached=1),
MDO(1, FPU, cached=0),
ChD(1),
ChD(2),
ZR_(2),
ChD(1),
ZR_(2),
ChD(1))
scheduler.start()
def main():
MDO = MDOCommand
UO_ = UOCommand
scheduler = Scheduler(ALU, FPU, BUS)
scheduler.add(
MDO(2, FPU, cached=True),
UO_(1, ALU, cached=False),
MDO(1, ALU, cached=True),
MDO(2, FPU, cached=False),
MDO(2, FPU, cached=True),
UO_(1, ALU, cached=True),
MDO(1, ALU, cached=True))
scheduler.start()
scheduler.add(
MDO(1, ALU, cached=False),
UO_(2, FPU, cached=False),
UO_(1, ALU, cached=True),
MDO(1, FPU, cached=False),
MDO(1, FPU, cached=False),
UO_(1, ALU, cached=False),
MDO(2, ALU, cached=True),
UO_(1, FPU, cached=True),
UO_(2, ALU, cached=True),
MDO(1, FPU, cached=False))
scheduler.start()
scheduler.add(
MDO(1, FPU, cached=True),
UO_(2, ALU, cached=False),
UO_(1, ALU, cached=True),
MDO(1, FPU, cached=True),
MDO(1, ALU, cached=False),
UO_(1, FPU, cached=False),
MDO(2, ALU, cached=False),
UO_(1, FPU, cached=True),
MDO(2, ALU, cached=False),
UO_(1, FPU, cached=False),
UO_(2, ALU, cached=False),
MDO(1, FPU, cached=True))
scheduler.start()
