def calibrate(verbose=False):
"""
Call Rurik's routine to calibrate the time delay at the adc interface.
"""
global zdok
adc5g.set_test_mode(roach2, 0)
adc5g.set_test_mode(roach2, 1)
adc5g.sync_adc(roach2)
save_zdok = zdok
set_zdok(0)
opt0, glitches0 = adc5g.calibrate_mmcm_phase(roach2, 0, \
[snap_name,])
if verbose or (opt0 == None):
print "zodk0 ", opt0, glitches0
else:
print "zodk0", opt0
set_zdok(1)
opt1, glitches1 = adc5g.calibrate_mmcm_phase(roach2, 1, \
[snap_name,])
if verbose or (opt1 == None):
print "zodk1 ", opt1, glitches1
else:
print "zodk1", opt1
set_zdok(save_zdok)
adc5g.unset_test_mode(roach2, 0)
adc5g.unset_test_mode(roach2, 1)
def setUpClass(cls):
TestBase.setUpClass()
adc5g.set_test_mode(cls._roach, cls._zdok_n)
adc5g.sync_adc(cls._roach)
cls._optimal_phase, cls._glitches = adc5g.calibrate_mmcm_phase(
cls._roach, cls._zdok_n, ["scope_raw_%d_snap" % cls._zdok_n]
)
def calibrate(verbose=False):
"""
Call Rurik's routine to calibrate the time delay at the adc interface.
"""
global zdok
adc5g.set_test_mode(roach2, 0)
adc5g.set_test_mode(roach2, 1)
adc5g.sync_adc(roach2)
save_zdok = zdok
set_zdok(0)
opt0, glitches0 = adc5g.calibrate_mmcm_phase(roach2, 0, \
[snap_name,])
if verbose or (opt0 == None):
print "zodk0 ", opt0, glitches0
else:
print "zodk0", opt0
set_zdok(1)
opt1, glitches1 = adc5g.calibrate_mmcm_phase(roach2, 1, \
[snap_name,])
if verbose or (opt1 == None):
print "zodk1 ", opt1, glitches1
else:
print "zodk1", opt1
set_zdok(save_zdok)
adc5g.unset_test_mode(roach2, 0)
adc5g.unset_test_mode(roach2, 1)
def deglitch(self):
'''
For use with adc5g test boffile. Calibrates phase of clock eye to see peaks
and troughs, not zero crossings.
'''
adc.set_test_mode(self._roach, 0)
adc.sync_adc(self._roach)
opt0, glitches0 = adc.calibrate_mmcm_phase(self._roach, 0,
['snapshot_adc0',])
adc.unset_test_mode(self._roach, 0)
def setUpClass(cls):
TestBase.setUpClass()
adc5g.set_test_mode(cls._roach,0)
adc5g.set_test_mode(cls._roach,1)
print "\nSETTING SYN"
adc5g.sync_adc(self._roach)
#cls._optimal_phase, cls._glitches = adc5g.calibrate_mmcm_phase(
#cls._roach, cls._zdok_n, ['scope_raw_%d_snap_bram' % cls._zdok_n])
adc5g.unset_test_mode(roach, 0)
adc5g.unset_test_mode(roach, 1)
def setUpClass(cls):
TestBase.setUpClass()
adc5g.set_test_mode(cls._roach, 0)
adc5g.set_test_mode(cls._roach, 1)
#adc5g.set_test_mode(cls._roach,1)
print "\nSETTING SYN"
#adc5g.sync_adc(self._roach)
# cls._optimal_phase, cls._glitches = adc5g.calibrate_mmcm_phase(
#cls._roach, cls._zdok_n, ['scope_raw_%d_snap_bram' % cls._zdok_n])
# cls._roach, cls._zdok_n, ['snap'])
#BOFFILE = 'adc5g_test.bof'
BOFFILE = 'adcethvfullv64zdk1_2015_Oct_09_1201.bof' #'adcethvfullv64_2015_Sep_09_0946.bof' #'adcethvfullv61_2015_Sep_02_1653.bof' #'adc5g_test_2014_Jul_21_2138.bof'#1649.bof' #'adc5g_test_rev2.bof'
ROACH = '192.168.100.182' #182 or 2
#ROACH = '10.0.1.213'
SNAPNAME = 'snap' #'scope_raw_0_snap'
def br(x):
return np.binary_repr(x, width=8)
r = corr.katcp_wrapper.FpgaClient(ROACH)
time.sleep(0.1)
#r.progdev(BOFFILE)
adc5g.set_test_mode(r, 0, counter=False)
adc5g.sync_adc(r)
adc5g.calibrate_all_delays(r, 0, snaps=[SNAPNAME], verbosity=5)
# adc5g.calibrate_mmcm_phase(r, 0, [SNAPNAME])
#adc5g.calibrate_mmcm_phase(r, 0, ['snap'])
adc5g.unset_test_mode(r, 0)
#a, b, c, d = adc5g.get_test_vector(r, ['snap'])
a, b, c, d = adc5g.get_test_vector(r, [SNAPNAME])
#x = adc5g.get_snapshot(r, 'scope_raw_0_snap')
#a = x[0::4]
#b = x[1::4]
#c = x[2::4]
#d = x[3::4]
for i in range(32):
print br(a[i]), br(b[i]), br(c[i]), br(d[i])
# for cn, core in enumerate([a,b,c,d]):
# pylab.plot(np.array(core) & 0xf, label='%d'%cn)
# pylab.legend()
#pylab.show()
# adc5g.unset_test_mode(roach, 0)
# adc5g.unset_test_mode(roach, 1)
# time.sleep(4)
print "\ntest finished"
def check_core_alignment(r,cores=4):
adc.set_spi_register(r,0,0x05+0x80,0) #use counter
adc.set_test_mode(r, 0)
adc.sync_adc(r,zdok_0=True,zdok_1=True)
test_vec = np.array(adc.get_test_vector(r, ['snapshot_adc0']))
#for i in range(1):
# for core in range(cores):
# print "%3d"%test_vec[core,i],
# print ''
s = test_vec[:,0]
if np.any(s==255): # Lazy way to make sure we aren't looking at a wrapping section of the counter
s = test_vec[100]
offset = np.min(s) - s #these are the relative arrival times. i.e. -1 means arrival is one clock too soon
return offset
def perform_mmcm_calibration(self):
"""
Perform MMCM calibration using Primiani's adc5g package.
"""
for snap_data in self.settings.snapshots_info:
adc5g.set_test_mode(self.fpga.fpga, snap_data['zdok'])
adc5g.sync_adc(self.fpga.fpga)
for snap_data in self.settings.snapshots_info:
print "Performing ADC5G MMCM calibration, ZDOK" + str(
snap_data['zdok']) + "..."
opt, glitches = adc5g.calibrate_mmcm_phase(self.fpga.fpga, \
snap_data['zdok'], snap_data['names'])
adc5g.unset_test_mode(self.fpga.fpga, snap_data['zdok'])
print "done"
def calibrate_adc(self):
# Set ADCs to test mode
for inp in SWARM_MAPPING_INPUTS:
set_test_mode(self.roach2, inp)
# Send a sync
sync_adc(self.roach2)
# Do the calibration
for inp in SWARM_MAPPING_INPUTS:
opt, glitches = calibrate_mmcm_phase(self.roach2, inp, [SWARM_SCOPE_SNAP % inp,])
if opt:
self.logger.info('ADC%d calibration found optimal phase: %d' % (inp, opt))
else:
self.logger.error('ADC%d calibration failed!' % inp)
# Unset test modes
for inp in SWARM_MAPPING_INPUTS:
unset_test_mode(self.roach2, inp)
def calibrate(verbose=False):
"""
Call Rurik's routine to calibrate the time delay at the adc interface.
"""
adc5g.set_test_mode(roach2, 0)
adc5g.set_test_mode(roach2, 1)
adc5g.sync_adc(roach2)
opt0, glitches0 = adc5g.calibrate_mmcm_phase(roach2, 0, \
['scope_raw_0_snap',])
if verbose or (opt0 == None):
print "zodk0 ", opt0, glitches0
else:
print "zodk0", opt0
opt1, glitches1 = adc5g.calibrate_mmcm_phase(roach2, 1, \
['scope_raw_1_snap',])
if verbose or (opt1 == None):
print "zodk1 ", opt1, glitches1
else:
print "zodk1", opt1
adc5g.unset_test_mode(roach2, 0)
adc5g.unset_test_mode(roach2, 1)
def calibrate(verbose=False):
"""
Call Rurik's routine to calibrate the time delay at the adc interface.
"""
adc5g.set_test_mode(roach2, 0)
adc5g.set_test_mode(roach2, 1)
adc5g.sync_adc(roach2)
opt0, glitches0 = adc5g.calibrate_mmcm_phase(roach2, 0, \
['scope_raw_0_snap',])
if verbose or (opt0 == None):
print "zodk0 ", opt0, glitches0
else:
print "zodk0", opt0
opt1, glitches1 = adc5g.calibrate_mmcm_phase(roach2, 1, \
['scope_raw_1_snap',])
if verbose or (opt1 == None):
print "zodk1 ", opt1, glitches1
else:
print "zodk1", opt1
adc5g.unset_test_mode(roach2, 0)
adc5g.unset_test_mode(roach2, 1)
print 'Programming FPGA with %s...' %bitstream,
if not opts.skip:
fpga.progdev(bitstream)
print 'done'
else:
print 'Skipped.'
print 'Configuring FFT shift register...',
fpga.write('shift_ctrl','\x00\x00\x0f\xff')
print 'done'
print 'Configuring accumulation period...',
fpga.write_int('acc_len',opts.acc_len)
print 'done'
# Calibrating ADCs
print 'Calibrating the time delay at the adc interface...'
adc5g.sync_adc(fpga)
opt1, glitches1 = adc5g.calibrate_mmcm_phase(fpga, 1,['snapshot_z1_c','snapshot_z1_a',])
#opt2, glitches2 = adc5g.calibrate_mmcm_phase(fpga, 0,['snapshot_z0_c','snapshot_z0_a',])
time.sleep(0.5)
print 'Resetting counters...',
fpga.write_int('cnt_rst',1)
fpga.write_int('cnt_rst',0)
print 'done'
print 'Setting digital gain of all channels to %i...'%opts.gain,
if not opts.skip:
fpga.write_int('gain',opts.gain) #write the same gain for all inputs, all channels
print 'done'
else:
print 'Skipped.'
def _start(self,
boffile='latest-build',
do_cal=True,
iface="p11p1",
verbose=10):
"""
Program bitcode on device.
Parameters
----------
boffile : string
Filename of the bitcode to program. If 'latest-build' then
use the current build. Default is 'latest-build'.
do_cal : bool
If true then do ADC core calibration. Default is True.
iface : string
Network interface connected to the data network.
verbose : int
The higher the more verbose, control the amount of output to
the screen. Default is 10 (probably the highest).
Returns
-------
"""
if boffile == "latest-build":
boffile = "r2daq_2016_May_18_1148.bof"
# program bitcode
self.roach2.progdev(boffile)
self.roach2.wait_connected()
if verbose > 1:
print "Bitcode '", boffile, "' programmed successfully"
# display clock speed
if verbose > 3:
print "Board clock is ", self.roach2.est_brd_clk(), "MHz"
# ADC interface calibration
if verbose > 3:
print "Performing ADC interface calibration... (only doing ZDOK0)"
adc5g.set_test_mode(self.roach2, 0)
#~ adc5g.set_test_mode(self.roach2, 1) #<<---- ZDOK1 not yet in bitcode
adc5g.sync_adc(self.roach2)
opt0, glitches0 = adc5g.calibrate_mmcm_phase(self.roach2, 0, [
'snap_0_snapshot',
])
#~ opt1, glitches1 = adc5g.calibrate_mmcm_phase(self.roach2, 1, ['zdok_1_snap_data',]) #<<---- ZDOK1 not yet in bitcode
adc5g.unset_test_mode(self.roach2, 0)
#~ adc5g.unset_test_mode(self.roach2, 1) #<<---- ZDOK1 not yet in bitcode
if verbose > 3:
print "...ADC interface calibration done."
if verbose > 5:
print "if0: opt0 = ", opt0, ", glitches0 = \n", array(glitches0)
#~ print "if1: ",opt0, glitches0 #<<---- ZDOK1 not yet in bitcode
# ADC core calibration
if do_cal:
self.calibrate_adc_ogp(zdok=0, verbose=verbose)
# build channel-list
ch_list = ['a', 'b', 'c', 'd', 'e', 'f']
self._implemented_digital_channels = []
for ch in ch_list:
try:
self.roach2.read_int("tengbe_{0}_ctrl".format(ch))
self._implemented_digital_channels.append(ch)
except RuntimeError:
pass
if verbose > 3:
print "Valid channels in this build: {0}".format(
self.implemented_digital_channels)
# hold master reset signal and arm the manual sync
self.roach2.write_int('master_ctrl', 0x00000001 | 0x00000002)
master_ctrl = self.roach2.read_int('master_ctrl')
# hold 10gbe reset signal
for ch in self.implemented_digital_channels:
self.roach2.write_int('tengbe_{0}_ctrl'.format(ch), 0x80000000)
# ip, port of data interface on receive side
dest_ip_str_cmp = ni.ifaddresses(iface)[2][0]['addr'].split('.')
ip3 = int(dest_ip_str_cmp[0])
ip2 = int(dest_ip_str_cmp[1])
ip1 = int(dest_ip_str_cmp[2])
ip0 = int(dest_ip_str_cmp[3])
dest_ip = (ip3 << 24) + (ip2 << 16) + (ip1 << 8) + ip0
dest_port = 4001
# fill arp table on ROACH2
mac_iface = ni.ifaddresses(iface)[17][0]['addr']
hex_iface = int(mac_iface.translate(None, ':'), 16)
arp = [0xffffffffffff] * 256
arp[ip0] = hex_iface
# and configure
ch_offset = 0
for ch in self.implemented_digital_channels:
# ip, port, mac of data interface on transmit side
src_ip = (ip3 << 24) + (ip2 << 16) + (ip1 << 8) + 2 + ch_offset
src_port = 4000
src_mac = (2 << 40) + (2 << 32) + src_ip
self.roach2.config_10gbe_core('tengbe_{0}_core'.format(ch),
src_mac, src_ip, src_port, arp)
self.roach2.write_int('tengbe_{0}_ip'.format(ch), dest_ip)
self.roach2.write_int('tengbe_{0}_port'.format(ch),
dest_port + ch_offset)
ch_offset = ch_offset + 1
# and release reset
for ch in self.implemented_digital_channels:
self.roach2.write_int('tengbe_{0}_ctrl'.format(ch), 0x00000000)
# set time, wait until just before a second boundary
while (abs(datetime.utcnow().microsecond - 9e5) > 1e3):
sleep(0.001)
# when the system starts running it will be the next second
ut0 = int(time()) + 1
self.roach2.write_int('unix_time0', ut0)
# release master reset signal
master_ctrl = self.roach2.read_int('master_ctrl')
master_ctrl = master_ctrl & 0xFFFFFFFC
self.roach2.write_int('master_ctrl', master_ctrl)
# # wait 100ms and then trigger start of manual sync
# sleep(0.1)
# master_ctrl = self.roach2.read_int('master_ctrl')
# master_ctrl = master_ctrl & 0xFFFFFFFC
# self.roach2.write_int('master_ctrl',master_ctrl)
# on the
if verbose > 1:
print "Configuration done, system should be running"
for delay in range(n_delays - max_zeros + 1):
print "DELAY %2d:" % delay,
for bit in range(n_bits):
print "%4d" % score[bit, delay],
print ''
ROACH = '192.168.0.111'
r = corr.katcp_wrapper.FpgaClient(ROACH)
time.sleep(0.1)
adc.set_spi_register(r, 0, 0x05 + 0x80, 1) #use strobing test mode
adc.set_test_mode(r, 0)
adc.set_test_mode(r, 1)
adc.sync_adc(r, zdok_0=True, zdok_1=False)
BITS = 8
DELAY_RANGE = 32
CORES = 4
glitches = np.zeros([CORES, BITS, DELAY_RANGE])
for delay in range(DELAY_RANGE):
print "setting delay %d" % (delay)
set_io_delay(r, 0, 0, delay)
set_io_delay(r, 0, 1, delay)
set_io_delay(r, 0, 2, delay)
set_io_delay(r, 0, 3, delay)
test_vec = np.array(adc.get_test_vector(r, ['snapshot_adc0']))
#for i in range(4096):
# print np.binary_repr(core_a[i],width=8),
# print np.binary_repr(core_b[i],width=8),
s = test_vec[100]
offset = np.min(s) - s #these are the relative arrival times. i.e. -1 means arrival is one clock too soon
return offset
ROACH = '192.168.0.111'
r = corr.katcp_wrapper.FpgaClient(ROACH)
time.sleep(0.1)
adc.set_spi_register(r,0,0x05+0x80,1) #use strobing test mode
adc.set_test_mode(r, 0)
adc.set_test_mode(r, 1)
adc.sync_adc(r,zdok_0=True,zdok_1=True)
BITS = 8
DELAY_RANGE = 32
CORES = 4
glitches = np.zeros([CORES,BITS,DELAY_RANGE])
for delay in range(DELAY_RANGE):
print "setting delay %d"%(delay)
set_io_delay(r,0,0,delay)
set_io_delay(r,0,1,delay)
set_io_delay(r,0,2,delay)
set_io_delay(r,0,3,delay)
test_vec = np.array(adc.get_test_vector(r, ['snapshot_adc0']))
#for i in range(4096):
# print np.binary_repr(core_a[i],width=8),
# print np.binary_repr(core_b[i],width=8),
import numpy as np
BOFFILE = 'adc5g_test_rev2.bof'
ROACH = '10.0.1.213'
SNAPNAME = 'scope_raw_0_snap'
def br(x):
return np.binary_repr(x, width=8)
r = corr.katcp_wrapper.FpgaClient(ROACH)
time.sleep(0.1)
r.progdev(BOFFILE)
adc5g.set_test_mode(r, 0, counter=False)
adc5g.sync_adc(r)
adc5g.calibrate_all_delays(r, 0, snaps=['snap'], verbosity=5)
#adc5g.calibrate_mmcm_phase(r, 0, ['snap'])
#adc5g.unset_test_mode(r, 0)
#a, b, c, d = adc5g.get_test_vector(r, ['snap'])
a, b, c, d = adc5g.get_test_vector(r, [SNAPNAME])
#x = adc5g.get_snapshot(r, 'scope_raw_0_snap')
#a = x[0::4]
#b = x[1::4]
#c = x[2::4]
#d = x[3::4]
for i in range(32):
print br(a[i]), br(b[i]), br(c[i]), br(d[i])
for cn, core in enumerate([a,b,c,d]):
def calibrate_gliches(fpga, snap_a, snapc, adc, current_channel):
if current_channel == 0:
adc5g.sync_adc(fpga)
opt1, glitches1 = adc5g.calibrate_mmcm_phase(fpga, adc, [snap_a, snapc])
def _start(self,boffile='latest-build',do_cal=True,iface="p11p1",verbose=10):
"""
Program bitcode on device.
Parameters
----------
boffile : string
Filename of the bitcode to program. If 'latest-build' then
use the current build. Default is 'latest-build'.
do_cal : bool
If true then do ADC core calibration. Default is True.
iface : string
Network interface connected to the data network.
verbose : int
The higher the more verbose, control the amount of output to
the screen. Default is 10 (probably the highest).
Returns
-------
"""
if boffile == "latest-build":
boffile = "r2daq_2016_May_18_1148.bof"
# program bitcode
self.roach2.progdev(boffile)
self.roach2.wait_connected()
if verbose > 1:
print "Bitcode '", boffile, "' programmed successfully"
# display clock speed
if verbose > 3:
print "Board clock is ", self.roach2.est_brd_clk(), "MHz"
# ADC interface calibration
if verbose > 3:
print "Performing ADC interface calibration... (only doing ZDOK0)"
adc5g.set_test_mode(self.roach2, 0)
#~ adc5g.set_test_mode(self.roach2, 1) #<<---- ZDOK1 not yet in bitcode
adc5g.sync_adc(self.roach2)
opt0, glitches0 = adc5g.calibrate_mmcm_phase(self.roach2, 0, ['snap_0_snapshot',])
#~ opt1, glitches1 = adc5g.calibrate_mmcm_phase(self.roach2, 1, ['zdok_1_snap_data',]) #<<---- ZDOK1 not yet in bitcode
adc5g.unset_test_mode(self.roach2, 0)
#~ adc5g.unset_test_mode(self.roach2, 1) #<<---- ZDOK1 not yet in bitcode
if verbose > 3:
print "...ADC interface calibration done."
if verbose > 5:
print "if0: opt0 = ",opt0, ", glitches0 = \n", array(glitches0)
#~ print "if1: ",opt0, glitches0 #<<---- ZDOK1 not yet in bitcode
# ADC core calibration
if do_cal:
self.calibrate_adc_ogp(zdok=0,verbose=verbose)
# build channel-list
ch_list = ['a','b','c','d','e','f']
self._implemented_digital_channels = []
for ch in ch_list:
try:
self.roach2.read_int("tengbe_{0}_ctrl".format(ch))
self._implemented_digital_channels.append(ch)
except RuntimeError:
pass
if verbose > 3:
print "Valid channels in this build: {0}".format(self.implemented_digital_channels)
# hold master reset signal and arm the manual sync
self.roach2.write_int('master_ctrl',0x00000001 | 0x00000002)
master_ctrl = self.roach2.read_int('master_ctrl')
# hold 10gbe reset signal
for ch in self.implemented_digital_channels:
self.roach2.write_int('tengbe_{0}_ctrl'.format(ch),0x80000000)
# ip, port of data interface on receive side
dest_ip_str_cmp = ni.ifaddresses(iface)[2][0]['addr'].split('.')
ip3 = int(dest_ip_str_cmp[0])
ip2 = int(dest_ip_str_cmp[1])
ip1 = int(dest_ip_str_cmp[2])
ip0 = int(dest_ip_str_cmp[3])
dest_ip = (ip3<<24) + (ip2<<16) + (ip1<<8) + ip0
dest_port = 4001
# fill arp table on ROACH2
mac_iface = ni.ifaddresses(iface)[17][0]['addr']
hex_iface = int(mac_iface.translate(None,':'),16)
arp = [0xffffffffffff] * 256
arp[ip0] = hex_iface
# and configure
ch_offset = 0
for ch in self.implemented_digital_channels:
# ip, port, mac of data interface on transmit side
src_ip = (ip3<<24) + (ip2<<16) + (ip1<<8) + 2+ch_offset
src_port = 4000
src_mac = (2<<40) + (2<<32) + src_ip
self.roach2.config_10gbe_core('tengbe_{0}_core'.format(ch),src_mac,src_ip,src_port,arp)
self.roach2.write_int('tengbe_{0}_ip'.format(ch),dest_ip)
self.roach2.write_int('tengbe_{0}_port'.format(ch),dest_port+ch_offset)
ch_offset = ch_offset + 1
# and release reset
for ch in self.implemented_digital_channels:
self.roach2.write_int('tengbe_{0}_ctrl'.format(ch),0x00000000)
# set time, wait until just before a second boundary
while(abs(datetime.utcnow().microsecond-9e5)>1e3):
sleep(0.001)
# when the system starts running it will be the next second
ut0 = int(time())+1
self.roach2.write_int('unix_time0',ut0)
# release master reset signal
master_ctrl = self.roach2.read_int('master_ctrl')
master_ctrl = master_ctrl & 0xFFFFFFFC
self.roach2.write_int('master_ctrl',master_ctrl)
# # wait 100ms and then trigger start of manual sync
# sleep(0.1)
# master_ctrl = self.roach2.read_int('master_ctrl')
# master_ctrl = master_ctrl & 0xFFFFFFFC
# self.roach2.write_int('master_ctrl',master_ctrl)
# on the
if verbose > 1:
print "Configuration done, system should be running"
s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
s.connect((TCP_IP,TCP_PORT))
print 'Connecting to %s'%opts.roach
r = corr.katcp_wrapper.FpgaClient(opts.roach)
time.sleep(0.2)
print 'ROACH is connected?', r.is_connected()
if opts.prog_fpga:
print 'Programming ROACH with boffile %s'%opts.boffile
r.progdev(opts.boffile)
time.sleep(0.5)
print 'Estimating clock speed...'
print 'Clock speed is %d MHz'%r.est_brd_clk()
print 'Calibrating ADCs'
adc.sync_adc(r)
adc.calibrate_all_delays(r,0,snaps=['snapshot_adc0'],verbosity=opts.verbosity)
adc.calibrate_all_delays(r,1,snaps=['snapshot_adc1'],verbosity=opts.verbosity)
adc.sync_adc(r)
adc.set_test_mode(r, 0)
adc.set_test_mode(r, 1)
adc.sync_adc(r)
opt0, glitches0 = adc.calibrate_mmcm_phase(r, 0, ['snapshot_adc0',])
opt1, glitches1 = adc.calibrate_mmcm_phase(r, 1, ['snapshot_adc1',])
print opt0, glitches0
print opt1, glitches1
adc.unset_test_mode(r, 0)
adc.unset_test_mode(r, 1)
print 'reseting control sw'
r.write_int('control',0)
def setUpClass(cls):
TestBase.setUpClass()
adc5g.set_test_mode(cls._roach, cls._zdok_n)
adc5g.sync_adc(cls._roach)
cls._optimal_phase, cls._glitches = adc5g.calibrate_mmcm_phase(
cls._roach, cls._zdok_n, ['scope_raw_%d_snap' % cls._zdok_n])
def _start(self,boffile='latest-build',do_cal=True,iface='enp11s0',verbose=10):
"""
Program bitcode on device.
Parameters
----------
boffile : string
Filename of the bitcode to program. If 'latest-build' then
use the current build. Default is 'latest-build'.
do_cal : bool
If true then do ADC core calibration. Default is True.
iface : string
Network interface connected to the data network.
verbose : int
The higher the more verbose, control the amount of output to
the screen. Default is 10 (probably the highest).
Returns
-------
"""
if boffile == "latest-build":
boffile = "he6_cres_correlator_2018_Sep_14_2002.bof"
# program bitcode
self.roach2.progdev(boffile)
self.roach2.wait_connected()
if verbose > 1:
print "Bitcode '", boffile, "' programmed successfully"
# display clock speed
if verbose > 3:
print "Board clock is ", self.roach2.est_brd_clk(), "MHz"
if self.roach2.est_brd_clk() > 250.0 or self.roach2.est_brd_clk()<199.0:
print "WrOnG INpuT cLoCK fREQuencY! trY AgAIN, FoOL!!!"
# ADC interface calibration
if verbose > 3:
print "Performing ADC interface calibration on ZDOK0"
adc5g.set_test_mode(self.roach2, 0)
adc5g.sync_adc(self.roach2)
opt0, glitches0 = adc5g.calibrate_mmcm_phase(self.roach2, 0, ['snap_0_snapshot',])
adc5g.unset_test_mode(self.roach2, 0)
print "Performing ADC interface calibration on ZDOK1"
adc5g.set_test_mode(self.roach2, 1)
adc5g.sync_adc(self.roach2)
opt1, glitches1 = adc5g.calibrate_mmcm_phase(self.roach2, 1, ['snap_1_snapshot',])
adc5g.unset_test_mode(self.roach2, 1)
if verbose > 3:
print "...ADC interface calibration done."
if verbose > 5:
print "if0: opt0 = ",opt0, ", glitches0 = \n", array(glitches0)
print "if1: opt1 = ",opt1, ", glitches0 = \n", array(glitches1)
# ADC core calibration
if do_cal:
self.calibrate_adc_ogp(zdok=0,verbose=verbose)
self.calibrate_adc_ogp(zdok=1,verbose=verbose)
# build channel-list
ch_list = ['a','b','c','d','e','f','g','h']
self._implemented_digital_channels = []
for ch in ch_list:
try:
self.roach2.read_int("tengbe_{0}_ctrl".format(ch))
self._implemented_digital_channels.append(ch)
except RuntimeError:
pass
if verbose > 3:
print "Valid channels in this build: {0}".format(self.implemented_digital_channels)
# hold master reset signal and arm the manual sync
self.roach2.write_int('master_ctrl',0x00000001 | 0x00000002)
master_ctrl = self.roach2.read_int('master_ctrl')
# hold 10gbe reset signal
self.roach2.write_int('tengbe_a_ctrl',0x80000000)
# ip, port of data interface on receive side
print "Establishing connection on interface 'enp11s0' with MAC address 4c:ed:fb:b4:35:3d"
print "If connection is invalid, call netifaces.interfaces() for a list of available interfaces"
dest_ip_str_cmp = ni.ifaddresses(iface)[2][0]['addr'].split('.')
ip3 = int(dest_ip_str_cmp[0])
ip2 = int(dest_ip_str_cmp[1])
ip1 = int(dest_ip_str_cmp[2])
ip0 = int(dest_ip_str_cmp[3])
#dest_ip = (ip3<<24) + (ip2<<16) + (ip1<<8) + ip0
#dest_ip = (ip3*2**24) + (ip2*2**16) + (ip1*2**8) + ip0
#dest_ip = -4294967296 + (ip3*2**24) + (ip2*2**16) + (ip1*2**8) + ip0
#dest_ip = (0<<32) + (ip3<<24) + (ip2<<16) + (ip1<<8) + ip0
dest_ip = (0*2**32) + (ip3*2**24) + (ip2*2**16) + (ip1*2**8) + ip0
print "Setting ROACH 10GbE output IP to",dest_ip
dest_port = 4001
print "Setting ROACH 10GbE output port to",dest_port
# fill arp table on ROACH2
mac_iface = ni.ifaddresses(iface)[17][0]['addr']
hex_iface = 84585013851453
arp = [0xffffffffffff] * 256
arp[ip0] = hex_iface
# ip, port, mac of data interface on transmit side
src_ip = (ip3<<24) + (ip2<<16) + (ip1<<8) + 2
src_port = 4000
src_mac = (2<<40) + (2<<32) + src_ip
self.roach2.config_10gbe_core('tengbe_a_core',src_mac,src_ip,src_port,arp)
self.roach2.write_int('tengbe_a_ip',dest_ip)
dest_ip_out = self.roach2.read_int("tengbe_a_ip")
self.roach2.write_int('tengbe_a_port',dest_port)
dest_port_out = self.roach2.read_int("tengbe_a_port")
print "ROACH 10GbE output now on IP",dest_ip_out,"and port",dest_port_out
# and release reset
self.roach2.write_int('tengbe_a_ctrl',0x00000000)
# set time, wait until just before a second boundary
while(abs(datetime.utcnow().microsecond-9e5)>1e3):
sleep(0.001)
# when the system starts running it will be the next second
ut0 = int(time())+1
self.roach2.write_int('unix_time0',ut0)
self.set_fft_shift('1101010101010', 'ab')
# release master reset signal
master_ctrl = self.roach2.read_int('master_ctrl')
master_ctrl = master_ctrl & 0xFFFFFFFC
self.roach2.write_int('master_ctrl',master_ctrl)
if verbose > 1:
print "Configuration done, system should be running"
for delay in range(n_delays-max_zeros+1):
print "DELAY %2d:" %delay,
for bit in range(n_bits):
print "%4d"%score[bit,delay],
print ''
ROACH = '192.168.0.111'
r = corr.katcp_wrapper.FpgaClient(ROACH)
time.sleep(0.1)
adc.set_spi_register(r,0,0x05+0x80,1) #use strobing test mode
adc.set_test_mode(r, 0)
adc.set_test_mode(r, 1)
adc.sync_adc(r,zdok_0=True,zdok_1=False)
BITS = 8
DELAY_RANGE = 32
CORES = 4
glitches = np.zeros([CORES,BITS,DELAY_RANGE])
for delay in range(DELAY_RANGE):
print "setting delay %d"%(delay)
set_io_delay(r,0,0,delay)
set_io_delay(r,0,1,delay)
set_io_delay(r,0,2,delay)
set_io_delay(r,0,3,delay)
test_vec = np.array(adc.get_test_vector(r, ['snapshot_adc0']))
#for i in range(4096):
# print np.binary_repr(core_a[i],width=8),
# print np.binary_repr(core_b[i],width=8),
s = socket.socket(socket.AF_INET, socket.SOCK_STREAM)
s.connect((TCP_IP, TCP_PORT))
print 'Connecting to %s' % opts.roach
r = corr.katcp_wrapper.FpgaClient(opts.roach)
time.sleep(0.2)
print 'ROACH is connected?', r.is_connected()
if opts.prog_fpga:
print 'Programming ROACH with boffile %s' % opts.boffile
r.progdev(opts.boffile)
time.sleep(0.5)
print 'Estimating clock speed...'
print 'Clock speed is %d MHz' % r.est_brd_clk()
print 'Calibrating ADCs'
adc.sync_adc(r)
adc.calibrate_all_delays(r,
0,
snaps=['snapshot_adc0'],
verbosity=opts.verbosity)
adc.calibrate_all_delays(r,
1,
snaps=['snapshot_adc1'],
verbosity=opts.verbosity)
adc.sync_adc(r)
adc.set_test_mode(r, 0)
adc.set_test_mode(r, 1)
adc.sync_adc(r)
opt0, glitches0 = adc.calibrate_mmcm_phase(r, 0, [
'snapshot_adc0',
])
if not roach2.wait_connected(timeout=args.timeout):
msg = "Could not establish connection to '{0}' within {1} seconds, aborting".format(
args.host,args.timeout)
raise RuntimeError(msg)
if args.verbose > 1:
print "programmed bitcode '{0}'".format(args.boffile)
# set data mux to ADC
roach2.write_int('r2dbe_data_mux_0_sel', 1)
roach2.write_int('r2dbe_data_mux_1_sel', 1)
# calibrate ADCs
adc5g.set_test_mode(roach2, 0)
adc5g.set_test_mode(roach2, 1)
adc5g.sync_adc(roach2)
opt, glitches = adc5g.calibrate_mmcm_phase(roach2, 0, ['r2dbe_snap_8bit_0_data',])
gstr = adc5g.pretty_glitch_profile(opt,glitches)
print "ADC0 calibration found optimal phase: {0:2d} [{1}]".format(opt,gstr)
opt, glitches = adc5g.calibrate_mmcm_phase(roach2, 1, ['r2dbe_snap_8bit_1_data',])
gstr = adc5g.pretty_glitch_profile(opt,glitches)
print "ADC1 calibration found optimal phase: {0:2d} [{1}]".format(opt,gstr)
adc5g.unset_test_mode(roach2, 0)
adc5g.unset_test_mode(roach2, 1)
# arm the one pps
roach2.write_int('r2dbe_onepps_ctrl', 1<<31)
roach2.write_int('r2dbe_onepps_ctrl', 0)
sleep(2)
# get 10 gbe destination MAC & IP
print 'Programming the R2DBE FPGA with firmware file r2dbe_rev2.bof...'
roach2.progdev(
'r2dbe_rev2.bof') # JanW: must do 'gzip -d r2dbe_rev2.bof.gz' manually
roach2.wait_connected()
else:
print 'Skipping R2DBE FPGA reconfiguration step, proceeding directly to settings change.'
# Set data mux to ADC
roach2.write_int('r2dbe_data_mux_0_sel', 1)
roach2.write_int('r2dbe_data_mux_1_sel', 1)
# Calibrate ADCs
print 'Calibrating ADC clock phase...'
adc5g.set_test_mode(roach2, 0)
adc5g.set_test_mode(roach2, 1)
adc5g.sync_adc(roach2)
opt, glitches = adc5g.calibrate_mmcm_phase(roach2, 0, [
'r2dbe_snap_8bit_0_data',
])
print 'Optimum and glitches for tested phase offsets on adc0:'
print opt, glitches
opt, glitches = adc5g.calibrate_mmcm_phase(roach2, 1, [
'r2dbe_snap_8bit_1_data',
])
print 'Optimum and glitches for tested phase offsets on adc1:'
print opt, glitches
adc5g.unset_test_mode(roach2, 0)
adc5g.unset_test_mode(roach2, 1)
# Set 10 gbe vals
for ip_idx, corename in ((0, 'tengbe_0'), (1, 'tengbe_1')):