DEPENDENCIES = ['demoaxi.v']
def __init__(self, data_w, addr_w, domain='sync'):
self.data_w = data_w
self.addr_w = addr_w
self.domain = domain
self.axilite = AxiLiteSlave(data_w, addr_w, name='S_AXI')
def elaborate(self, platform):
m = Module()
m.submodules.demoaxi_i = Instance(
'demoaxi',
p_C_S_AXI_DATA_WIDTH=self.data_w,
p_C_S_AXI_ADDR_WIDTH=self.addr_w,
i_S_AXI_ACLK=ClockSignal(self.domain),
i_S_AXI_ARESETN=~ResetSignal(self.domain),
**get_ports_for_instance(self.axilite, prefix='S_AXI_'),
)
if isinstance(platform, Platform):
for d in self.DEPENDENCIES:
add_verilog_file(platform, d)
return m
if __name__ == '__main__':
from amaranth.cli import main
core = DemoAxi(32, 8)
ports = [v for v in core.axilite.fields.values()]
main(core, None, ports=ports)
from amaranth import *
from amaranth.cli import main
class System(Elaboratable):
def __init__(self):
self.adr = Signal(16)
self.dat_r = Signal(8)
self.dat_w = Signal(8)
self.we = Signal()
def elaborate(self, platform):
m = Module()
m.submodules.cpu = Instance(
"CPU",
p_RESET_ADDR=0xfff0,
i_d_adr=self.adr,
i_d_dat_r=self.dat_r,
o_d_dat_w=self.dat_w,
i_d_we=self.we,
)
return m
if __name__ == "__main__":
sys = System()
main(sys, ports=[sys.adr, sys.dat_r, sys.dat_w, sys.we])
from amaranth import *
from amaranth.cli import main
class ALU(Elaboratable):
def __init__(self, width):
self.sel = Signal(2)
self.a = Signal(width)
self.b = Signal(width)
self.o = Signal(width)
self.co = Signal()
def elaborate(self, platform):
m = Module()
with m.If(self.sel == 0b00):
m.d.comb += self.o.eq(self.a | self.b)
with m.Elif(self.sel == 0b01):
m.d.comb += self.o.eq(self.a & self.b)
with m.Elif(self.sel == 0b10):
m.d.comb += self.o.eq(self.a ^ self.b)
with m.Else():
m.d.comb += Cat(self.o, self.co).eq(self.a - self.b)
return m
if __name__ == "__main__":
alu = ALU(width=16)
main(alu, ports=[alu.sel, alu.a, alu.b, alu.o, alu.co])
i_S_AXI_ACLK=ClockSignal(self.domain),
i_S_AXI_ARESETN=~ResetSignal(self.domain),
**self.get_instance_ports(),
)
if isinstance(platform, Platform):
for d in self.DEPENDENCIES:
add_verilog_file(platform, d)
return m
if __name__ == '__main__':
from amaranth.cli import main
xbar = AxiLiteXBar(32, 16)
slave1 = AxiLiteSlave(32, 16, name='slave1')
slave2 = AxiLiteSlave(32, 16, name='slave2')
master1 = AxiLiteMaster(32, 16, name='master1')
master2 = AxiLiteMaster(32, 16, name='master2')
xbar.add_slave(slave1, 0x8000, 0x1000)
xbar.add_slave(slave2, 0x9000, 0x1000)
xbar.add_master(master1)
xbar.add_master(master2)
ports = [v for v in slave1.fields.values()]
ports += [v for v in slave2.fields.values()]
ports += [v for v in master1.fields.values()]
ports += [v for v in master2.fields.values()]
main(xbar, None, ports=ports)
from amaranth import *
from amaranth.cli import main
class ParMux(Elaboratable):
def __init__(self, width):
self.s = Signal(3)
self.a = Signal(width)
self.b = Signal(width)
self.c = Signal(width)
self.o = Signal(width)
def elaborate(self, platform):
m = Module()
with m.Switch(self.s):
with m.Case("--1"):
m.d.comb += self.o.eq(self.a)
with m.Case("-1-"):
m.d.comb += self.o.eq(self.b)
with m.Case("1--"):
m.d.comb += self.o.eq(self.c)
with m.Case():
m.d.comb += self.o.eq(0)
return m
if __name__ == "__main__":
pmux = ParMux(width=16)
main(pmux, ports=[pmux.s, pmux.a, pmux.b, pmux.c, pmux.o])
from amaranth import *
from amaranth.cli import main
class ClockDivisor(Elaboratable):
def __init__(self, factor):
self.v = Signal(factor)
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m
if __name__ == "__main__":
m = Module()
m.domains.sync = sync = ClockDomain("sync", async_reset=True)
m.submodules.ctr = ctr = ClockDivisor(factor=16)
main(m, ports=[ctr.o, sync.clk])
from amaranth import *
from amaranth.lib.cdc import FFSynchronizer
from amaranth.cli import main
i, o = Signal(name="i"), Signal(name="o")
m = Module()
m.submodules += FFSynchronizer(i, o)
if __name__ == "__main__":
main(m, ports=[i, o])
from amaranth import *
from amaranth.cli import main
class RegisterFile(Elaboratable):
def __init__(self):
self.adr = Signal(4)
self.dat_r = Signal(8)
self.dat_w = Signal(8)
self.we = Signal()
self.mem = Memory(width=8, depth=16, init=[0xaa, 0x55])
def elaborate(self, platform):
m = Module()
m.submodules.rdport = rdport = self.mem.read_port()
m.submodules.wrport = wrport = self.mem.write_port()
m.d.comb += [
rdport.addr.eq(self.adr),
self.dat_r.eq(rdport.data),
wrport.addr.eq(self.adr),
wrport.data.eq(self.dat_w),
wrport.en.eq(self.we),
]
return m
if __name__ == "__main__":
rf = RegisterFile()
main(rf, ports=[rf.adr, rf.dat_r, rf.dat_w, rf.we])
from amaranth import *
from amaranth.cli import main
class GPIO(Elaboratable):
def __init__(self, pins, bus):
self.pins = pins
self.bus = bus
def elaborate(self, platform):
m = Module()
m.d.comb += self.bus.r_data.eq(self.pins[self.bus.addr])
with m.If(self.bus.we):
m.d.sync += self.pins[self.bus.addr].eq(self.bus.w_data)
return m
if __name__ == "__main__":
bus = Record([
("addr", 3),
("r_data", 1),
("w_data", 1),
("we", 1),
])
pins = Signal(8)
gpio = GPIO(Array(pins), bus)
main(gpio, ports=[pins, bus.addr, bus.r_data, bus.w_data, bus.we])
from amaranth import *
from amaranth.cli import main
m = Module()
cd_por = ClockDomain(reset_less=True)
cd_sync = ClockDomain()
m.domains += cd_por, cd_sync
delay = Signal(range(256), reset=255)
with m.If(delay != 0):
m.d.por += delay.eq(delay - 1)
m.d.comb += [
ClockSignal().eq(cd_por.clk),
ResetSignal().eq(delay != 0),
]
if __name__ == "__main__":
main(m, ports=[cd_por.clk])
#
# Copyright (c) 2021 Hans Baier <*****@*****.**>
# SPDX-License-Identifier: CERN-OHL-W-2.0
#
import sys
from amaranth.cli import main
from adat import *
if __name__ == "__main__":
modulename = sys.argv[1]
sys.argv[1] = "generate"
if modulename == "nrzidecoder":
module = NRZIDecoder(100e6)
main(module,
name="nrzi_decoder",
ports=[module.nrzi_in, module.data_out])
elif modulename == "receiver":
r = ADATReceiver(100e6)
main(r,
name="adat_receiver",
ports=[
r.clk, r.reset_in, r.adat_in, r.addr_out, r.sample_out,
r.output_enable, r.user_data_out
])
elif modulename == "transmitter":
t = ADATTransmitter()
main(t,
name="adat_transmitter",
ports=[
t.addr_in,
with m.State("DATA"):
with m.If(stb):
m.d.sync += [
bit.eq(bit - 1),
self.data.eq(Cat(self.i, self.data))
]
with m.If(bit == 0):
m.next = "STOP"
with m.State("STOP"):
with m.If(stb):
with m.If(self.i):
m.next = "DONE"
with m.Else():
m.next = "ERROR"
with m.State("DONE"):
m.d.comb += self.rdy.eq(1)
with m.If(self.ack):
m.next = "START"
m.d.comb += self.err.eq(fsm.ongoing("ERROR"))
with m.State("ERROR"):
pass
return m
if __name__ == "__main__":
rx = UARTReceiver(20)
main(rx, ports=[rx.i, rx.data, rx.rdy, rx.ack, rx.err])
from amaranth import *
from amaranth.cli import main
class Counter(Elaboratable):
def __init__(self, width):
self.v = Signal(width, reset=2**width - 1)
self.o = Signal()
def elaborate(self, platform):
m = Module()
m.d.sync += self.v.eq(self.v + 1)
m.d.comb += self.o.eq(self.v[-1])
return m
ctr = Counter(width=16)
if __name__ == "__main__":
main(ctr, ports=[ctr.o])
with m.If(audio_fifo_right.r_rdy & adat_transmitter.ready_out):
m.d.sync += [
adat_transmitter.valid_in.eq(1),
adat_transmitter.sample_in.eq(
audio_fifo_right.r_data << 8),
adat_transmitter.addr_in.eq(1),
adat_transmitter.last_in.eq(1)
]
m.next = "IDLE"
with m.Else():
m.d.sync += adat_transmitter.valid_in.eq(0),
# wire up ADAT transmitter
m.d.comb += [
adat_transmitter.user_data_in.eq(0),
self.adat_out.eq(adat_transmitter.adat_out),
]
return m
if __name__ == "__main__":
m = SynthModule()
main(m,
name="synthmodule",
ports=[
m.midi_stream.valid, m.midi_stream.payload,
ClockSignal("adat"),
ResetSignal("adat"), m.adat_out
])
