def jt51_process():
yield Tick("jt51")
yield Tick("jt51")
yield Tick("jt51")
yield Tick("jt51")
yield dut.jt51_stream.ready.eq(1)
for _ in range(50):
yield Tick("jt51")
def process():
for i, f in zip(inputs, filters):
yield self.dut.operands.valid.eq(1)
yield self.dut.operands.payload['inputs'].eq(
Cat(*[Const(x, signed(8)) for x in i]))
yield self.dut.operands.payload['filters'].eq(
Cat(*[Const(x, signed(8)) for x in f]))
yield Tick()
while (yield self.dut.operands.ready) != 1:
yield Tick()
yield self.dut.operands.valid.eq(0)
def midi_message(*args, set_valid=True):
if set_valid:
yield valid.eq(1)
yield payload.eq(args[0] >> 4)
yield Tick("usb")
for byte in args:
yield payload.eq(byte)
yield Tick("usb")
yield payload.eq(0)
if set_valid:
yield valid.eq(0)
def adat_process():
bitcount :int = 0
for bit in testdata_nrzi: #[224:512 * 2]:
if (bitcount == 4 * 256 + 64):
yield dut.invalid_frame_in.eq(1)
yield Tick("adat")
yield dut.invalid_frame_in.eq(0)
for _ in range(20):
yield Tick("adat")
else:
yield dut.invalid_frame_in.eq(0)
yield dut.nrzi_in.eq(bit)
yield Tick("adat")
bitcount += 1
def sysex(*args):
yield valid.eq(1)
for byte in args:
yield payload.eq(byte)
yield Tick("usb")
yield payload.eq(0)
yield valid.eq(0)
def adat_process():
nrzi = []
i = 0
while i < 1800:
yield Tick("adat")
out = yield dut.adat_out
nrzi.append(out)
i += 1
# skip initial zeros
nrzi = nrzi[nrzi.index(1):]
signal = decode_nrzi(nrzi)
decoded = adat_decode(signal)
print(decoded)
user_bits = [decoded[frame][0] for frame in range(7)]
assert user_bits == [0x0, 0xf, 0xa, 0xb, 0xc, 0xd,
0xe], print_assert_failure(user_bits)
assert decoded[0][1:] == [0, 0, 0, 0, 0, 0, 0,
0], print_assert_failure(decoded[0][1:])
assert decoded[1][1:] == [0, 1, 2, 3, 0xc, 0xd, 0xe,
0xf], print_assert_failure(decoded[1][1:])
assert decoded[2][1:] == [
0x10, 0x20, 0x30, 0x40, 0x50, 0x60, 0x70, 0x80
], print_assert_failure(decoded[2][1:])
assert decoded[3][1:] == [
0x100, 0x200, 0x300, 0x400, 0x500, 0x600, 0x700, 0x800
], print_assert_failure(decoded[3][1:])
assert decoded[4][1:] == [
0x1000, 0x2000, 0x3000, 0x4000, 0x5000, 0x6000, 0x7000, 0x8000
], print_assert_failure(decoded[4][1:])
assert decoded[5][1:] == [
0x10000, 0x20000, 0x30000, 0x40000, 0x50000, 0x60000, 0x70000,
0x80000
], print_assert_failure(decoded[5][1:])
def sync_process():
yield Tick("sync")
yield Tick("sync")
yield dut.user_data_in.eq(0xf)
for i in range(4):
yield from write(i, i, drop_valid=True)
for i in range(4):
yield from write(4 + i, 0xc + i, i == 3, drop_valid=True)
yield dut.user_data_in.eq(0xa)
yield Tick("sync")
for i in range(8):
yield from write(i, (i + 1) << 4, i == 7)
yield dut.user_data_in.eq(0xb)
yield Tick("sync")
for i in range(8):
yield from write(i, (i + 1) << 8, i == 7)
yield dut.user_data_in.eq(0xc)
yield Tick("sync")
for i in range(8):
yield from write(i, (i + 1) << 12, i == 7)
yield dut.user_data_in.eq(0xd)
yield Tick("sync")
for i in range(8):
yield from write(i, (i + 1) << 16, i == 7)
yield dut.user_data_in.eq(0xe)
yield Tick("sync")
for i in range(8):
yield from write(i, (i + 1) << 20, i == 7, drop_valid=True)
yield from wait(900)
def process():
for (a_word, b_word, enable, clear), expected in DATA:
yield dut.a_word.eq(a_word)
yield dut.b_word.eq(b_word)
yield dut.enable.eq(enable)
yield dut.clear.eq(clear)
yield Delay(0.1) # Wait for input values to settle
# Check on accumulator, as calcuated last cycle
self.assertEqual(expected, (yield dut.accumulator))
yield Tick()
def sync_process():
# Obtain the output data
out_data = []
for _ in range(int(clockratio) * no_cycles):
yield Tick("sync")
if (yield dut.data_out_en == 1):
bit = yield dut.data_out
yield out_data.append(bit)
#
# Validate output
#
# omit a 1 at the end of the sync pad
out_data = out_data[1:]
# Whenever the state machine switches from SYNC to DECODE we need to omit the first 11 sync bits
validate_output(out_data[:256 - 12], one_empty_adat_frame()[12:256])
out_data = out_data[256-12:]
validate_output(out_data[:256], sixteen_adat_frames[:256])
out_data = out_data[256:]
# now the adat stream was interrupted, it continues to output zeroes, until it enters the SYNC state
validate_output(out_data[:10], interrupted_adat_stream[:10])
out_data = out_data[10:]
# followed by 2 well formed adat frames
# omit the first 11 sync bits
validate_output(out_data[:256 - 12], sixteen_adat_frames[256 + 12:2 * 256])
out_data = out_data[256 - 12:]
validate_output(out_data[:256], sixteen_adat_frames[2 * 256:3 * 256])
out_data = out_data[256:]
# followed by one invalid frame - the state machine SYNCs again
# followed by 13 well-formed frames
# omit the first 11 sync bits
validate_output(out_data[:256 - 12], sixteen_adat_frames[3 * 256 + 12:4 * 256])
out_data = out_data[256-12:]
for i in range(4, 16):
validate_output(out_data[:256], sixteen_adat_frames[i * 256:(i + 1) * 256])
out_data = out_data[256:]
print("Success!")
def write(addr: int,
sample: int,
last: bool = False,
drop_valid: bool = False):
while (yield dut.ready_out == 0):
yield from wait(1)
if last:
yield dut.last_in.eq(1)
yield dut.addr_in.eq(addr)
yield dut.sample_in.eq(sample)
yield dut.valid_in.eq(1)
yield Tick("sync")
if drop_valid:
yield dut.valid_in.eq(0)
if last:
yield dut.last_in.eq(0)
def sync_process():
# Obtain the output data
out_data = [[0 for x in range(9)] for y in range(16)] #store userdata in the 9th column
sample = 0
for _ in range(int(clockratio) * no_cycles):
yield Tick("sync")
if (yield dut.output_enable == 1):
channel = yield dut.addr_out
out_data[sample][channel] = yield dut.sample_out
if (channel == 7):
out_data[sample][8] = yield dut.user_data_out
sample += 1
#print(out_data)
#
# The receiver needs 2 sync pads before it starts outputting data:
# * The first sync pad is needed for the nrzidecoder to sync
# * The second sync pad is needed for the receiver to sync
# Therefore each time after the connection was lost the first frame will be lost while syncing.
# In our testdata we loose the initial one_empty_adat_frame and the second sample (#1, count starts with 0)
#
sampleno = 0
for i in range(16):
if (sampleno == 1): #skip the first frame while the receiver syncs after an interruption
sampleno += 1
elif (sampleno == 16): #ensure the data ended as expected
assert out_data[i] == [0, 0, 0, 0, 0, 0, 0, 0, 0], "Sample {} was: {}".format(sampleno, print_frame(out_data[sampleno]))
else:
assert out_data[i] == [((0 << 20) | sampleno), ((1 << 20) | sampleno), ((2 << 20) | sampleno),
((3 << 20) | sampleno), ((4 << 20) | sampleno), ((5 << 20) | sampleno),
((6 << 20) | sampleno), ((7 << 20) | sampleno), 0b0101]\
, "Sample #{} was: {}".format(sampleno, print_frame(out_data[sampleno]))
sampleno += 1
print("Success!")
def adat_process():
for bit in testdata_nrzi: # [224:512 * 2]:
yield dut.adat_in.eq(bit)
yield Tick("adat")
def usb_process():
for _ in range(2**10 - 200):
yield Tick("usb")
yield valid.eq(0)
yield payload.eq(0)
yield dut.midi_stream.ready.eq(1)
yield Tick("usb")
yield payload.eq(0x0b)
yield Tick("usb")
yield Tick("usb")
yield valid.eq(1)
yield Tick("usb")
yield payload.eq(0xb0)
yield Tick("usb")
yield payload.eq(0x01)
yield Tick("usb")
yield valid.eq(0)
yield payload.eq(0x00)
yield Tick("usb")
yield Tick("usb")
yield payload.eq(0x0b)
yield Tick("usb")
yield Tick("usb")
yield valid.eq(1)
yield from midi_message(0xb0, 0x01, 0x03)
yield valid.eq(0)
yield Tick("usb")
yield Tick("usb")
yield from midi_message(0x93, 69, 0x7f)
yield Tick("usb")
yield from midi_message(0x83, 69, 0x00)
yield Tick("usb")
yield Tick("usb")
yield from midi_message(0x93, 60, 0x7f)
yield from midi_message(0x83, 60, 0x00)
yield Tick("usb")
yield Tick("usb")
yield Tick("usb")
yield Tick("usb")
for _ in range(128):
yield Tick("usb")
# send USB MIDI sysex
yield from sysex(0x04, 0xf0, 0x0a, 0x0b, 0x07, 0x0c, 0x0d, 0xf7)
for _ in range(40):
yield Tick("usb")
yield dut.midi_stream.valid.eq(1)
yield from midi_message(0x93, 60, 0x7f, set_valid=False)
yield Tick("usb")
yield from midi_message(0x93, 61, 0x7f, set_valid=False)
yield dut.midi_stream.valid.eq(0)
for _ in range(128):
yield Tick("usb")
def wait(n_cycles: int):
for _ in range(int(clockratio) * n_cycles):
yield Tick("sync")