def set_tstop(self):
"""
Add define statement to specify tstop
"""
if self.cfg.tstop is not None:
self.content.defines.append(
Define(name='TSTOP_MSDSL', value=self.cfg.tstop))
def __init__(self, prj_cfg: EmuConfig, cfg_file, prj_root):
super().__init__(cfg_file=cfg_file,
prj_root=prj_root,
build_root=prj_cfg.build_root,
name='msdsl')
self.include_statements += ['`include "msdsl.sv"']
# Parse command line arguments specific to MSDSL
self.args = None
self._parse_args()
# Initialize Parameters
self.dt = prj_cfg.cfg.dt
# Initialize msdsl config
self.cfg.model_dir = os.path.join(self._build_root, 'models')
# Update msdsl config with msdsl section in config file
self.cfg.update_config(subsection=self._name)
# Add defines according to command line arguments
if self.args.float:
self.add_define(Define(name='FLOAT_REAL', fileset='sim'))
if self.args.range_assertions:
self.add_define(Define(name='RANGE_ASSERTIONS', fileset='sim'))
if self.args.add_saturation:
self.add_define(Define(name='ADD_SATURATION'))
###############################################################
# Execute actions according to command line arguments
###############################################################
# make models
if self.args.models:
self.models()
def _parseconfig(self, cfg: dict, cfg_path: str):
"""
Store all entries from source.yaml to the according fileset or added to the list of additional config paths,
which will be read and stored in the next iteration.
:param cfg: source.yaml stored as dict
:param cfg_path: path to source.yaml file
"""
if 'verilog_sources' in cfg.keys(): # Add verilog sources to filesets
print(f'Verilog Sources: {[key for key in cfg["verilog_sources"].keys()]}')
for verilog_source in cfg['verilog_sources'].keys():
self._verilog_sources.append(VerilogSource(files=cfg['verilog_sources'][verilog_source]['files'],
fileset=cfg['verilog_sources'][verilog_source]['fileset'] if 'fileset' in cfg['verilog_sources'][verilog_source].keys() else 'default',
config_path=cfg_path,
version=cfg['verilog_sources'][verilog_source]['version'] if 'version' in cfg['verilog_sources'][verilog_source].keys() else None,
name=verilog_source))
if 'verilog_headers' in cfg.keys(): # Add verilog headers to filesets
print(f'Verilog Headers: {[key for key in cfg["verilog_headers"].keys()]}')
for verilog_header in cfg['verilog_headers'].keys():
self._verilog_headers.append(VerilogHeader(files=cfg['verilog_headers'][verilog_header]['files'],
fileset=cfg['verilog_headers'][verilog_header]['fileset'] if 'fileset' in cfg['verilog_headers'][verilog_header].keys() else 'default',
config_path=cfg_path,
name=verilog_header))
if 'vhdl_sources' in cfg.keys(): # Add VHDL sources to filesets
print(f'VHDL Sources: {[key for key in cfg["vhdl_sources"].keys()]}')
for vhdl_source in cfg['vhdl_sources'].keys():
self._vhdl_sources.append(VHDLSource(files=cfg['vhdl_sources'][vhdl_source]['files'],
fileset=cfg['vhdl_sources'][vhdl_source]['fileset'] if 'fileset' in cfg['vhdl_sources'][vhdl_source].keys() else 'default',
config_path=cfg_path,
library=cfg['vhdl_sources'][vhdl_source]['library'] if 'library' in cfg['vhdl_sources'][vhdl_source].keys() else None,
version = cfg['vhdl_sources'][vhdl_source]['version'] if 'version' in cfg['vhdl_sources'][vhdl_source].keys() else None,
name=vhdl_source))
if 'edif_files' in cfg.keys(): # Add EDIF files to filesets
print(f'EDIF Files: {[key for key in cfg["edif_files"].keys()]}')
for edif_file in cfg['edif_files'].keys():
self._edif_files.append(EDIFFile(files=cfg['edif_files'][edif_file]['files'],
fileset=cfg['edif_files'][edif_file]['fileset'] if 'fileset' in cfg['edif_files'][edif_file].keys() else 'default',
config_path=cfg_path,
name=edif_file))
if 'firmware_files' in cfg.keys(): # Add firmware files to filesets
print(f'Firmware Files: {[key for key in cfg["firmware_files"].keys()]}')
for firmware_file in cfg['firmware_files'].keys():
self._firmware_files.append(FirmwareFile(files=cfg['firmware_files'][firmware_file]['files'],
fileset=cfg['firmware_files'][firmware_file]['fileset'] if 'fileset' in cfg['firmware_files'][firmware_file].keys() else 'default',
config_path=cfg_path,
name=firmware_file))
if 'xci_files' in cfg.keys(): # Add xci files to filesets
print(f'XCI Files: {[key for key in cfg["xci_files"].keys()]}')
for xci_file in cfg['xci_files'].keys():
self._xci_files.append(XCIFile(files=cfg['xci_files'][xci_file]['files'],
fileset=cfg['xci_files'][xci_file]['fileset'] if 'fileset' in cfg['xci_files'][xci_file].keys() else 'default',
config_path=cfg_path,
name=xci_file))
if 'xdc_files' in cfg.keys(): # Add constraint files to filesets
print(f'XDC Files: {[key for key in cfg["xdc_files"].keys()]}')
for xdc_file in cfg['xdc_files'].keys():
self._xdc_files.append(XDCFile(files=cfg['xdc_files'][xdc_file]['files'],
fileset=cfg['xdc_files'][xdc_file]['fileset'] if 'fileset' in cfg['xdc_files'][xdc_file].keys() else 'default',
config_path=cfg_path,
name=xdc_file))
if 'mem_files' in cfg.keys(): # Add mem files to filesets
print(f'Mem Files: {[key for key in cfg["mem_files"].keys()]}')
for mem_file in cfg['mem_files'].keys():
self._mem_files.append(MEMFile(files=cfg['mem_files'][mem_file]['files'],
fileset=cfg['mem_files'][mem_file]['fileset'] if 'fileset' in cfg['mem_files'][mem_file].keys() else 'default',
config_path=cfg_path,
name=mem_file))
if 'bd_files' in cfg.keys(): # Add block diagram files to filesets
print(f'Block Diagram Files: {[key for key in cfg["bd_files"].keys()]}')
for bd_file in cfg['bd_files'].keys():
self._bd_files.append(BDFile(files=cfg['bd_files'][bd_file]['files'],
fileset=cfg['bd_files'][bd_file]['fileset'] if 'fileset' in cfg['bd_files'][bd_file].keys() else 'default',
config_path=cfg_path,
name=bd_file))
if 'ip_repos' in cfg.keys(): # Add IP repositories to filesets
print(f'IP Repos: {[key for key in cfg["ip_repos"].keys()]}')
for ip_repo in cfg['ip_repos'].keys():
self._ip_repos.append(IPRepo(files=cfg['ip_repos'][ip_repo]['files'],
fileset=cfg['ip_repos'][ip_repo]['fileset'] if 'fileset' in cfg['ip_repos'][ip_repo].keys() else 'default',
config_path=cfg_path,
name=ip_repo))
if 'functional_models' in cfg.keys(): # Add functional model to filesets
print(f'Functional Models: {[key for key in cfg["functional_models"].keys()]}')
for functional_model in cfg['functional_models'].keys():
func_model = FunctionalModel(files=cfg['functional_models'][functional_model]['files'],
fileset=cfg['functional_models'][functional_model]['fileset'] if 'fileset' in cfg['functional_models'][functional_model].keys() else 'default',
config_path=cfg_path,
name=functional_model)
func_model.set_gen_files_path(hdl_dir_root=self.root_func_models)
self._functional_models.append(func_model)
if 'sub_configs' in cfg.keys(): # Add sub config files to filesets
for sub_config in cfg['sub_configs'].keys():
self._sub_config_paths.append(SubConfig(files=cfg['sub_configs'][sub_config]['files'], config_path=cfg_path, name=sub_config))
if 'defines' in cfg.keys(): # Add defines to filesets
print(f'Defines: {[key for key in cfg["defines"].keys()]}')
for define in cfg['defines'].keys():
self._defines.append(Define(name=cfg['defines'][define]['name'],
value=cfg['defines'][define]['value'] if 'value' in cfg['defines'][define].keys() else None,
fileset=cfg['defines'][define]['fileset'] if 'fileset' in cfg['defines'][define].keys() else 'default'))
def _setup_filesets(self):
"""
Finalize filesets for the project. Before this function is called, all sources should have been added to the
project, either via source.yaml files/plugin-specific includes, or interactively via the add_sources function.
Note: Do not add more sources to the project after this function has been run; They will only be considered,
if this function is executed again afterwards.
"""
# Read source.yaml files and store in fileset object
default_filesets = ['default'] + self.cpu_targets + self.fpga_targets
self.filesets = Filesets(
root=self.args.input,
default_filesets=default_filesets,
root_func_models=self._prj_cfg.build_root_functional_models)
self.filesets.read_filesets()
# Add Defines and Sources from plugins
for plugin in self._plugins:
plugin._setup_sources()
plugin._setup_defines()
self.filesets._defines += plugin._dump_defines()
self.filesets._verilog_sources += plugin._dump_verilog_sources()
self.filesets._verilog_headers += plugin._dump_verilog_headers()
self.filesets._vhdl_sources += plugin._dump_vhdl_sources()
# Add custom source and define objects here e.g.:
config_path = os.path.join(self.args.input, 'source.yaml')
# Add some default files depending on whether there is a custom top level
for fileset in self.cpu_targets + self.fpga_targets:
try:
custom_top = self.cfg_file[ConfigSections.CPU_TARGET][fileset][
'custom_top'] if fileset in self.cpu_targets else self.cfg_file[
ConfigSections.FPGA_TARGET][fileset]['custom_top']
print(f'Using custom top for fileset {fileset}.')
except:
custom_top = False
if not custom_top:
#ToDo: check if file inclusion should be target specific -> less for simulation only for example
self.filesets.add_source(source=VerilogSource(
files=os.path.join(self.args.input, 'tb.sv'),
config_path=config_path,
fileset=fileset,
name='tb'))
# Set define variables specifying the emulator control architecture
# TODO: find a better place for these operations, and try to avoid directly accessing the config dictionary
for fileset in self.cpu_targets + self.fpga_targets:
try:
top_module = self.cfg_file[ConfigSections.CPU_TARGET][fileset][
'top_module'] if fileset in self.cpu_targets else self.cfg_file[
ConfigSections.FPGA_TARGET][fileset]['top_module']
except:
top_module = 'top'
print(f'Using top module {top_module} for fileset {fileset}.')
self.filesets.add_define(
define=Define(name='CLK_MSDSL',
value=f'{top_module}.clk_default_osc',
fileset=fileset))
self.filesets.add_define(
define=Define(name='CKE_MSDSL',
value=f'{top_module}.emu_cke',
fileset=fileset))
self.filesets.add_define(
define=Define(name='RST_MSDSL',
value=f'{top_module}.emu_rst',
fileset=fileset))
self.filesets.add_define(
define=Define(name='DT_WIDTH',
value=f'{self._prj_cfg.cfg.dt_width}',
fileset=fileset))
self.filesets.add_define(
define=Define(name='DT_SCALE',
value=f'{self._prj_cfg.cfg.dt_scale}',
fileset=fileset))
self.filesets.add_define(
define=Define(name='TIME_WIDTH',
value=f'{self._prj_cfg.cfg.time_width}',
fileset=fileset))
self.filesets.add_define(
define=Define(name='EMU_DT',
value=f'{self._prj_cfg.cfg.dt}',
fileset=fileset))
self.filesets.add_define(
define=Define(name='DEC_WIDTH',
value=f'{self._prj_cfg.cfg.dec_bits}',
fileset=fileset))
self.filesets.add_define(
define=Define(name='EMU_CLK_FREQ',
value=f'{self._prj_cfg.cfg.emu_clk_freq}',
fileset=fileset))
# Set cpu target specific defines
for fileset in self.cpu_targets:
self.filesets.add_define(
define=Define(name='SIMULATION_MODE_MSDSL', fileset=fileset))
def _setup_defines(self):
"""
Add Define objects that are specific to MSDSL
"""
self.add_define(Define(name='DT_MSDSL', value=self.dt))
self.add_define(Define(name='SIMULATION_MODE_MSDSL', fileset='sim'))
def add_saturation(self):
self._add_define(Define(name='ADD_SATURATION'))
def range_assertions(self):
self._add_define(Define(name='RANGE_ASSERTIONS', fileset='sim'))
def float(self):
self._add_define(Define(name='FLOAT_REAL', fileset='sim'))