def prepare(self):
""" Preparation of ifxxcelium Camino wrapper script"""
if "ifxxcelium" in self.cfg.xcelium_config.xrun:
cmd = []
cmd += ['ifxxcelium', 'prepare', '-uc', 'rtl']
if self.unit:
cmd += ["-unit", self.unit]
if self.id:
cmd += ["-id", self.id]
else:
self.id = "xcelium"
print(cmd)
call(cmd, cwd=self.cfg.build_root)
makefile = os.environ[
"WORKAREA"] + "/units/" + self.unit + "/simulation/" + self.id + "/Makefile"
if "PHONY: inicio" not in open(makefile, 'r').read():
self.patch_makefile(makefile)
else:
print(
"inicio make target already in Makefile, will not patch it"
)
else:
print("No ifxxcelium script detected, nothing to prepare..")
def view(self):
# build command
#cmd = ['open', '/Applications/Scansion.app', self.target.cfg['vcd_path']]
cmd = ['open', '/Applications/Scansion.app']
# run command
call(cmd)
def run(self, filename=r'run.tcl', err_str=None):
# write the TCL script
tcl_script = Path(self.target.prj_cfg.build_root).resolve() / filename
self.write_to_file(tcl_script)
# assemble the command
cmd = [str(self.xsct), str(tcl_script)]
# run the script
call(args=cmd, err_str=err_str)
def view(self):
# build command
if os.path.isfile(self.target.cfg.vcd_path):
cmd = [self.cfg.simvision_config.simvision, '-wave', self.target.cfg.vcd_path]
cmd[1:1] = self.cfg.simvision_config.lsf_opts.split()
# add waveform file if it exists
if self.cfg.simvision_config.svcf_config is not None:
if os.path.isfile(self.cfg.simvision_config.svcf_config):
cmd.extend(['-input', self.cfg.simvision_config.svcf_config])
# run command
call(cmd)
else:
raise Exception(f'ERROR: Result file: {self.target.cfg.vcd_path} does not exist; cannot open waveforms!')
def view(self, result_file=None):
vcd_path = result_file if result_file is not None else self.target.cfg.vcd_path
# build command
if os.path.isfile(vcd_path):
cmd = [self.cfg.gtkwave_config.gtkwave, vcd_path]
cmd[1:1] = self.cfg.gtkwave_config.lsf_opts.split()
# add waveform file if it exists
if self.cfg.gtkwave_config.gtkw_config is not None:
if os.path.isfile(self.cfg.gtkwave_config.gtkw_config):
cmd.append(self.cfg.gtkwave_config.gtkw_config)
# run command
call(cmd)
else:
raise Exception(
f'ERROR: Result file: {vcd_path} does not exist; cannot open waveforms!'
)
def compile(self):
# build up the simulation command
cmd = [self.cfg.icarus_config.iverilog, '-g2012', '-o', self.cfg.icarus_config.output_file_path, '-s',
self.target.cfg.top_module]
# if desired, only preprocess
if self.cfg.cfg.preprocess_only:
cmd.append('-E')
# add defines
for define in self.target.content.defines:
for k, v in define.define.items():
if v is not None:
cmd.extend(['-D', f"{k}={v}"])
else:
cmd.extend(['-D', f"{k}"])
# add include directories, remove filename from paths and create a list of inc dirs removing duplicates
inc_dirs = set()
for sources in self.target.content.verilog_headers:
for src in sources.files:
inc_dirs.add(os.path.dirname(src))
for inc_dir in inc_dirs:
cmd.extend(['-I', inc_dir])
# add verilog source files
for sources in self.target.content.verilog_sources:
for src in sources.files:
cmd.append(src)
# add HDL files for functional models
for sources in self.target.content.functional_models:
for src in sources.gen_files:
cmd.append(src)
# add any additional user-supplied flags
for flag in self.flags:
cmd.append(str(flag))
# run iverilog
call(cmd, cwd=self.cfg.build_root)
def models(self):
"""
Call gen.py to generate analog models.
"""
# make model directory, removing the old one if necessary
rm_rf(self.cfg.model_dir)
mkdir_p(self.cfg.model_dir)
# run generator script
gen_script = os.path.join(self._prj_root, 'gen.py')
if 'PYTHON_MSDSL' in os.environ:
python_name = os.environ['PYTHON_MSDSL']
else:
python_name = which('python')
call([
python_name, gen_script, '-o', self.cfg.model_dir, '--dt',
str(self.dt)
])
def run(self,
filename=r"run.tcl",
nolog=True,
nojournal=True,
stack=None,
interactive=False,
err_str=None):
# write the TCL script
tcl_script = os.path.join(self.target.prj_cfg.build_root, filename)
self.write_to_file(tcl_script)
# assemble the command
cmd = []
cmd += [self.target.prj_cfg.vivado_config.vivado]
# Specify stack size if needed. Xilinx suggests this
# can sometimes fix segfault issues:
# https://www.xilinx.com/support/answers/64434.html
if stack:
cmd += ['-stack', f'{stack}']
# run mode
if interactive:
cmd += ['-mode', 'tcl']
else:
cmd += ['-mode', 'batch']
# script location
cmd += ['-source', tcl_script]
# inserting lsf_opts after vivado call:
cmd[1:1] = self.target.prj_cfg.vivado_config.lsf_opts.split()
if nolog:
cmd.append('-nolog')
if nojournal:
cmd.append('-nojournal')
# run the script
call(args=cmd, cwd=self.target.prj_cfg.build_root, err_str=err_str)
def models(self):
"""
Call gen.py to generate analog models.
"""
# make model directory, removing the old model directory if necessary
rm_rf(self._build_root)
# run generator script
if 'PYTHON_MSDSL' in os.environ:
python_name = os.environ['PYTHON_MSDSL']
else:
python_name = which('python')
for generator_source in self.generator_sources:
# make model directory if necessary
mkdir_p(
os.path.join(self._build_root, generator_source.fileset,
generator_source.name))
for file in generator_source.files:
call([
python_name, file, '-o',
os.path.join(self._build_root, generator_source.fileset,
generator_source.name), '--dt',
str(self.dt)
])
def run(self):
args = [self.cfg.icarus_config.vvp, self.cfg.icarus_config.output_file_path]
cwd = self.cfg.build_root
err_str = re.compile('^(ERROR|FATAL):')
call(args, cwd=cwd, err_str=err_str)
def simulate(self, licqueue=True, smartorder=True, timescale='1ns/1ps'):
# prepare ifxxcelium makefile by adding inicio target
self.prepare()
# build up the simulation command
cmd = []
cmd += [self.cfg.xcelium_config.xrun]
if "ifxxcelium" in self.cfg.xcelium_config.xrun:
cmd += self.target.prj_cfg.xcelium_config.lsf_opts.split()
cmd += ['inicio']
if self.unit:
cmd += ["-unit", self.unit]
if self.id:
cmd += ["-id", self.id]
cmd += ['--']
cmd += ['-top', self.target.cfg.top_module]
cmd += ['-input', self.cfg.xcelium_config.tcl_input_path]
# order independent compilation for VHDL
if smartorder:
cmd += ['-smartorder']
# wait to get a license
if licqueue:
cmd += ['-licqueue']
# specify the default timescale
if timescale is not None:
cmd += ['-timescale', f'{timescale}']
# 64-bit or 32-bit mode
# TODO: is this actually necessary? the problem is that sometimes xrun is submitted through a bsub command,
# so the remote machine architecture isn't necessarily the same as that of the local machine that submits
# the job.
if '64bit' in platform.architecture():
cmd += ['-64bit']
# add defines
for define in self.target.content.defines:
for k, v in define.define.items():
if v is not None:
cmd.append(f"+define+{k}={v}")
else:
cmd.append(f"+define+{k}")
# add include directories, remove filename from paths and create a list of inc dirs removing duplicates
inc_dirs = set()
for sources in self.target.content.verilog_headers:
for src in sources.files:
inc_dirs.add(os.path.dirname(src))
for inc_dir in inc_dirs:
cmd.extend(['-incdir', inc_dir])
# add Verilog source files
for sources in self.target.content.verilog_sources:
for src in sources.files:
cmd.append(src)
# add HDL sources for functional models
for sources in self.target.content.functional_models:
for src in sources.gen_files:
cmd.append(src)
# add VHDL source files
# TODO: is it actually necessary to consolidate makelib commands together? if subsequent makelib commands
# append rather than replace files, then it should be OK (and simpler) to have a separate makelib for
# each file in each library.
libraries = OrderedDict()
for sources in self.target.content.vhdl_sources:
library = sources.library
if library not in libraries:
libraries[library] = []
files = sources.files
libraries[library] += files
for library, sources in libraries.items():
if library is not None:
cmd += ['-makelib', library]
else:
cmd += ['-makelib']
cmd += sources
cmd += ['-endlib']
# add any additional user-supplied flags
for flag in self.flags:
cmd.append(str(flag))
# write TCL file
with open(self.cfg.xcelium_config.tcl_input_path, 'w') as f:
f.write('run\n')
f.write('exit\n')
# run xrun
print(cmd)
call(cmd, cwd=self.cfg.build_root)
