def setUp(self):
self.bus = Apb3Bus(duration=APB3_DURATION)
self.s = WhiteboxSim(self.bus)
self.fifo_args = {'width': 32, 'depth': self.fifo_depth}
self.whitebox_args = {'interp': self.interp}
if not hasattr(self, 'i_gain'):
self.i_gain = 1.0
self.q_gain = 1.0
def test_rx(self):
bus = Apb3Bus(duration=APB3_DURATION)
s = WhiteboxSim(bus)
fifo_args = {
'width': 32,
'depth': 1024,
}
whitebox_args = {
'decim': 128,
}
def test_whitebox_rx():
return s.cosim_dut("cosim_whitebox_rx", fifo_args, whitebox_args)
@instance
def stimulus():
yield bus.reset()
yield whitebox_clear(bus)
yield bus.transmit(WR_DECIM_ADDR, 128)
yield bus.transmit(WE_FCW_ADDR, 100)
yield bus.receive(WR_DECIM_ADDR)
assert bus.rdata == 128
yield bus.receive(WE_FCW_ADDR)
assert bus.rdata == 100
s.start_receive()
yield bus.delay(1)
yield bus.transmit(WR_STATUS_ADDR, WRS_RXEN)
yield bus.receive(WR_STATUS_ADDR)
assert bus.rdata & WRS_RXEN
yield bus.dma_receive(s.rx_dmaready, WR_SAMPLE_ADDR, 8)
self.rx_data = bus.rdata
raise StopSimulation
rx_signal = np.zeros(1024, dtype=np.complex64)
rx_signal[0] = (1 << 8) + 1j * (1 << 8)
s.rx_signal(rx_signal)
s.simulate_rx(stimulus, test_whitebox_rx)
y = np.zeros(8, dtype=np.complex64)
y[0] = (1 << 8) + 1j * (1 << 8)
assert (s.rx(self.rx_data) == y).all()
def test_rx_overrun(self):
bus = Apb3Bus(duration=APB3_DURATION)
s = WhiteboxSim(bus)
fifo_args = {
'width': 32,
'depth': 1024,
}
whitebox_args = {
'decim': 128,
}
def test_whitebox_rx_overrun():
return s.cosim_dut("cosim_whitebox_rx_overrun", fifo_args,
whitebox_args)
@instance
def stimulus():
yield bus.reset()
yield whitebox_clear(bus)
yield bus.transmit(WR_DECIM_ADDR, 1)
yield bus.transmit(WE_FCW_ADDR, 100)
yield bus.receive(WR_DECIM_ADDR)
assert bus.rdata == 1
yield bus.receive(WE_FCW_ADDR)
assert bus.rdata == 100
s.start_receive()
yield bus.delay(1)
yield bus.transmit(WR_STATUS_ADDR, WRS_RXEN)
yield bus.receive(WR_STATUS_ADDR)
assert bus.rdata & WRS_RXEN
yield bus.delay(int(2048 * (40 / 6.)))
yield bus.receive(WR_RUNS_ADDR)
assert bus.rdata > 0
raise StopSimulation
rx_signal = np.zeros(2048 / 4, dtype=np.complex64)
s.rx_signal(rx_signal)
s.simulate_rx(stimulus, test_whitebox_rx_overrun, sample_rate=6.144e6)
def test_apb3_transaction(self):
bus = Apb3Bus(duration=APB3_DURATION)
s = WhiteboxSim(bus)
fifo_args = {'width': 32, 'depth': 1024}
whitebox_args = {
'interp': 200,
}
def test_whitebox_apb3_transaction():
return s.cosim_dut("cosim_whitebox_apb3_transaction", fifo_args,
whitebox_args)
@instance
def stimulus():
yield bus.reset()
yield bus.transmit(WE_INTERP_ADDR, 20)
yield bus.transmit(WE_FCW_ADDR, 100)
yield bus.receive(WE_INTERP_ADDR)
assert bus.rdata == 20
yield bus.receive(WE_FCW_ADDR)
assert bus.rdata == 100
yield bus.receive(WE_GAIN_ADDR)
gain_i, gain_q = bus.rdata & 0x3ff, (bus.rdata & 0x03ff0000) >> 16
assert (gain_i / 2.**9) == 1. # Default is 1
assert (gain_q / 2.**9) == 1. # Default is 1
gain_word = lambda i: intbv(
((intbv(int(i[1] * 2.**9))[32:] << 16) & 0x03ff0000) |
(intbv(int(i[0] * 2.**9))[32:] & 0x3ff))[32:]
yield bus.transmit(WE_GAIN_ADDR, gain_word((0.75, 1.25)))
yield bus.receive(WE_GAIN_ADDR)
gain_i, gain_q = bus.rdata & 0x3ff, (bus.rdata & 0x03ff0000) >> 16
assert (gain_i / 2.**9) == 0.75
assert (gain_q / 2.**9) == 1.25
raise StopSimulation
s.simulate(stimulus, test_whitebox_apb3_transaction)
def test_loop(self):
INTERP = 1
FIFO_DEPTH = 64
BULK_SIZE = 16
CNT = 512
bus = Apb3Bus(duration=APB3_DURATION)
s = WhiteboxSim(bus)
sample_rate = 10.24e6
freq = 100e3
n = np.arange(0, CNT)
x = (np.cos(freq * (2 * pi) * n / sample_rate) * (2**15-1)) + \
(np.sin(freq * (2 * pi) * n / sample_rate) * (2**15-1)) * 1j
fifo_args = {'width': 32, 'depth': FIFO_DEPTH}
whitebox_args = {'interp': INTERP}
def test_whitebox_loop():
return s.cosim_dut("cosim_whitebox_loop", fifo_args, whitebox_args)
@instance
def stimulus():
N = Signal(intbv(0)[32:])
yield bus.reset()
# Send a clear
yield whitebox_clear(bus)
yield bus.transmit(WE_STATUS_ADDR, WS_LOOPEN)
yield bus.receive(WR_STATUS_ADDR)
assert bus.rdata & WS_LOOPEN
yield bus.transmit(WE_INTERP_ADDR, 1)
sample = concat(intbv(1 << 6)[16:], intbv(1 << 6)[16:])
yield bus.transmit(WE_SAMPLE_ADDR, sample)
yield bus.transmit(WE_STATUS_ADDR, WES_TXSTOP)
yield bus.transmit(WE_STATUS_ADDR, WES_TXEN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WS_LOOPEN
yield bus.transmit(WR_DECIM_ADDR, 1)
yield bus.transmit(WR_STATUS_ADDR, WRS_RXSTOP)
yield bus.transmit(WR_STATUS_ADDR, WRS_RXEN)
yield bus.receive(WR_STATUS_ADDR)
while not bus.rdata & WRS_DATA:
yield bus.delay(1)
yield bus.receive(WR_STATUS_ADDR)
assert not (bus.rdata & WRS_RXEN)
yield bus.receive(WR_SAMPLE_ADDR)
print bus.rdata
yield bus.receive(WR_SAMPLE_ADDR)
print bus.rdata
assert bus.rdata == 0xdeadbeef
raise StopSimulation
s.simulate(stimulus, test_whitebox_loop, sample_rate=sample_rate)
def test_overrun_underrun(self):
INTERP = 200
FIFO_DEPTH = 4
bus = Apb3Bus(duration=APB3_DURATION)
s = WhiteboxSim(bus)
fifo_args = {'width': 32, 'depth': FIFO_DEPTH}
whitebox_args = {'interp': INTERP}
def test_whitebox_overrun_underrun():
return s.cosim_dut("cosim_whitebox_overrun_underrun", fifo_args,
whitebox_args)
@instance
def stimulus():
N = Signal(intbv(0)[32:])
yield bus.reset()
# Send a clear
yield whitebox_clear(bus)
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
yield bus.transmit(WE_THRESHOLD_ADDR,
concat(intbv(1)[16:],
intbv(3)[16:]))
yield bus.receive(WE_THRESHOLD_ADDR)
assert bus.rdata == concat(intbv(1)[16:], intbv(3)[16:])
yield bus.transmit(WE_INTERP_ADDR, INTERP)
yield bus.receive(WE_INTERP_ADDR)
assert bus.rdata == INTERP
## Insert samples until overrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0x0000ffff):
x = intbv(int(sin(1000 * (2 * pi) * N / 50000) * 2**15),
min=-2**15,
max=2**15)[16:]
yield bus.transmit(WE_SAMPLE_ADDR, concat(x, x))
N.next = N + 1
yield bus.receive(WE_RUNS_ADDR)
# Check that we're full
yield bus.receive(WE_STATUS_ADDR)
assert not (bus.rdata & WES_SPACE)
assert bus.rdata & WES_DATA
## Now start transmitting
yield bus.transmit(WE_STATUS_ADDR, WES_TXEN)
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_TXEN
## Wait until underrun
yield bus.receive(WE_RUNS_ADDR)
while not (bus.rdata & 0xffff0000):
yield bus.delay(1000)
yield bus.receive(WE_RUNS_ADDR)
## Make sure we're both over and underrun
assert bus.rdata & 0xffff0000 and bus.rdata & 0x0000ffff
# Check the fifo flags
yield bus.receive(WE_STATUS_ADDR)
assert bus.rdata & WES_SPACE
assert not (bus.rdata & WES_DATA)
raise StopSimulation
s.simulate(stimulus, test_whitebox_overrun_underrun)
rfe_enable = True
clearn = ResetSignal(0, 0, async=True)
clear_enable = Signal(bool(0))
dac2x_clock = Signal(bool(0))
dac_clock = Signal(bool(0))
dac_data = Signal(intbv(0)[10:])
dac_en = Signal(bool(0))
adc_idata = Signal(intbv(0, min=-2**9, max=2**9))
adc_qdata = Signal(intbv(0, min=-2**9, max=2**9))
tx_status_led = Signal(bool(0))
tx_dmaready = Signal(bool(1))
rx_status_led = Signal(bool(0))
rx_dmaready = Signal(bool(1))
bus = Apb3Bus()
bus_presetn = bus.presetn
bus_pclk = bus.pclk
bus_paddr = bus.paddr
bus_psel = bus.psel
bus_penable = bus.penable
bus_pwrite = bus.pwrite
bus_pwdata = bus.pwdata
bus_pslverr = bus.pslverr
bus_pready = bus.pready
bus_prdata = bus.prdata
fir_coeff_ram = Ram2(clearn, dac_clock, bus.pclk)
fir_delay_line_i_ram = Ram(clearn, dac_clock, dac_clock)
fir_delay_line_q_ram = Ram(clearn, dac_clock, dac_clock)
def test_rx(self):
bus = Apb3Bus(duration=APB3_DURATION)
s = WhiteboxSim(bus)
self.duration = 200e-6 # uS
self.sample_rate = 6.144e6
self.decim = 128
# Input signal
self.cnt = int(ceil(self.sample_rate * self.duration))
self.n = np.arange(self.cnt)
rx_signal = np.zeros(self.cnt, dtype=np.complex64)
for i in range(self.decim):
rx_signal[i] = (1 << 8) + 1j * (1 << 8)
s.rx_signal(rx_signal)
print "LENGTH IS", self.cnt
# Expected output signal
self.y = np.zeros(ceil(self.cnt / self.decim), dtype=np.complex64)
self.y[0] = (1 << 8) + 1j * (1 << 8)
fifo_args = {
'width': 32,
'depth': 1024,
}
whitebox_args = {
'decim': 128,
}
def test_whitebox_rx():
return s.cosim_dut("cosim_whitebox_rx", fifo_args, whitebox_args)
@instance
def stimulus():
yield bus.reset()
yield whitebox_clear(bus)
yield bus.transmit(WR_DECIM_ADDR, self.decim)
yield bus.transmit(WE_FCW_ADDR, 100)
yield bus.receive(WR_DECIM_ADDR)
assert bus.rdata == self.decim
yield bus.receive(WE_FCW_ADDR)
assert bus.rdata == 100
yield bus.delay(1)
s.start_receive()
yield bus.transmit(WR_STATUS_ADDR, WRS_RXEN)
yield bus.receive(WR_STATUS_ADDR)
assert bus.rdata & WRS_RXEN
yield bus.dma_receive(s.rx_dmaready, WR_SAMPLE_ADDR, len(self.y))
self.rx_data = bus.rdata
while not s.receive_done():
yield bus.delay(1)
raise StopSimulation
s.simulate_rx(stimulus, test_whitebox_rx, sample_rate=self.sample_rate)
actual_duration = s.rx_duration()
err = abs(self.duration - actual_duration / 1e9)
print 'Asserting RX duration...', self.duration, actual_duration / 1e9, err
assert err < .01 * self.duration, "Times are expected=%s actual=%s" % (
self.duration, actual_duration / 1e9)
rx = s.rx(self.rx_data)
print "Expected length", len(self.y), self.y
print "Actual length", len(rx), rx
assert (s.rx(self.rx_data) == self.y).all()