def from_bitarray(instr, processor):
imm11 = substring(instr, 10, 0)
j2 = bit_at(instr, 11)
j1 = bit_at(instr, 13)
imm10 = substring(instr, 25, 16)
s = bit_at(instr, 26)
i1 = bit_not(j1 ^ s, 1)
i2 = bit_not(j2 ^ s, 1)
imm32 = sign_extend(
chain(s, chain(i1, chain(i2, chain(imm10, imm11 << 1, 12), 22),
23), 24), 25, 32)
if processor.in_it_block() and not processor.last_in_it_block():
print('unpredictable')
else:
return BT4(instr, imm32=imm32)
def execute(self, processor):
if processor.condition_passed():
result, carry, overflow = add_with_carry(
processor.registers.get(self.n), bit_not(self.imm32, 32), 1)
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def execute(self, processor):
if processor.condition_passed():
result = processor.registers.get(self.n) | bit_not(self.imm32, 32)
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = self.carry
def from_bitarray(instr, processor):
imm11 = substring(instr, 10, 0)
j2 = bit_at(instr, 11)
j1 = bit_at(instr, 13)
imm10 = substring(instr, 25, 16)
s = bit_at(instr, 26)
i1 = bit_not(j1 ^ s, 1)
i2 = bit_not(j2 ^ s, 1)
imm32 = sign_extend(
chain(s, chain(i1, chain(i2, chain(imm10, imm11 << 1, 12), 22),
23), 24), 25, 32)
target_instr_set = processor.registers.current_instr_set()
if processor.in_it_block() and not processor.last_in_it_block():
print('unpredictable')
else:
return BlBlxImmediateT1(instr,
target_instr_set=target_instr_set,
imm32=imm32)
def execute(self, processor):
shift_n = lower_chunk(processor.registers.get(self.s), 8)
shifted = shift(processor.registers.get(self.m), 32, self.shift_t,
shift_n, processor.registers.cpsr.c)
result, carry, overflow = add_with_carry(
processor.registers.get(self.n), bit_not(shifted, 32), 1)
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def execute(self, processor):
shift_n = lower_chunk(processor.registers.get(self.s), 8)
shifted, carry = shift_c(processor.registers.get(self.m), 32,
self.shift_t, shift_n,
processor.registers.cpsr.c)
result = processor.registers.get(self.n) & bit_not(shifted, 32)
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
def execute(self, processor):
if processor.condition_passed():
shifted, carry = shift_c(processor.registers.get(self.m), 32,
self.shift_t, self.shift_n,
processor.registers.cpsr.c)
result = processor.registers.get(self.n) | bit_not(shifted, 32)
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
def execute(self, processor):
if processor.condition_passed():
result = bit_not(self.imm32, 32)
if self.d == 15:
processor.alu_write_pc(result)
else:
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = self.carry
def execute(self, processor):
if processor.condition_passed():
result, carry, overflow = add_with_carry(bit_not(processor.registers.get(self.n), 32), self.imm32, 1)
if self.d == 15:
processor.alu_write_pc(result)
else:
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def from_bitarray(instr, processor):
h = bit_at(instr, 0)
imm10l = substring(instr, 10, 1)
j2 = bit_at(instr, 11)
j1 = bit_at(instr, 13)
imm10h = substring(instr, 25, 16)
s = bit_at(instr, 26)
i1 = bit_not(j1 ^ s, 1)
i2 = bit_not(j2 ^ s, 1)
imm32 = sign_extend(
chain(s,
chain(i1, chain(i2, chain(imm10h, imm10l << 2, 12), 22), 23),
24), 25, 32)
target_instr_set = InstrSet.ARM
if processor.registers.current_instr_set() == InstrSet.THUMB_EE or h:
raise UndefinedInstructionException()
elif processor.in_it_block() and not processor.last_in_it_block():
print('unpredictable')
else:
return BlBlxImmediateT2(instr,
target_instr_set=target_instr_set,
imm32=imm32)
def execute(self, processor):
if processor.condition_passed():
shifted = shift(processor.registers.get(self.m), 32, self.shift_t,
self.shift_n, processor.registers.cpsr.c)
result, carry, overflow = add_with_carry(
processor.registers.get_sp(), bit_not(shifted, 32), 1)
if self.d == 15:
processor.alu_write_pc(result)
else:
processor.registers.set(self.d, result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
processor.registers.cpsr.c = carry
processor.registers.cpsr.v = overflow
def execute(self, processor):
if processor.condition_passed():
if (processor.registers.current_mode_is_user_or_system()
or processor.registers.current_instr_set()
== InstrSet.THUMB_EE):
print('unpredictable')
else:
operand2 = self.imm32
result = add_with_carry(processor.registers.get(self.n),
bit_not(operand2, 32), 1)[0]
if (processor.registers.cpsr.m == 0b11010
and processor.registers.cpsr.j
and processor.registers.cpsr.t):
print('unpredictable')
else:
processor.branch_write_pc(result)
def execute(self, processor):
if processor.condition_passed():
if processor.registers.current_mode_is_hyp():
raise UndefinedInstructionException()
elif processor.registers.current_mode_is_user_or_system():
print('unpredictable')
else:
operand2 = shift(processor.registers.get(
self.m), 32, self.shift_t, self.shift_n,
processor.registers.cpsr.c
) if self.register_form else self.imm32
if self.opcode == 0b0000:
result = processor.registers.get(self.n) & operand2
elif self.opcode == 0b0001:
result = processor.registers.get(self.n) ^ operand2
elif self.opcode == 0b0010:
result = add_with_carry(processor.registers.get(self.n),
bit_not(operand2, 32), 1)[0]
elif self.opcode == 0b0011:
result = add_with_carry(
bit_not(processor.registers.get(self.n), 32), operand2,
1)[0]
elif self.opcode == 0b0100:
result = add_with_carry(processor.registers.get(self.n),
operand2, 0)[0]
elif self.opcode == 0b0101:
result = add_with_carry(processor.registers.get(self.n),
operand2,
processor.registers.cpsr.c)[0]
elif self.opcode == 0b0110:
result = add_with_carry(processor.registers.get(self.n),
bit_not(operand2, 32),
processor.registers.cpsr.c)[0]
elif self.opcode == 0b0111:
result = add_with_carry(
bit_not(processor.registers.get(self.n), 32), operand2,
processor.registers.cpsr.c)[0]
elif self.opcode == 0b1100:
result = processor.registers.get(self.n) | operand2
elif self.opcode == 0b1101:
result = operand2
elif self.opcode == 0b1110:
result = processor.registers.get(self.n) & bit_not(
operand2, 32)
elif self.opcode == 0b1111:
result = bit_not(operand2, 32)
processor.registers.cpsr_write_by_instr(
processor.registers.get_spsr(), 0b1111, True)
if processor.registers.cpsr.m == 0b11010 and processor.registers.cpsr.j and processor.registers.cpsr.t:
print('unpredictable')
else:
processor.branch_write_pc(result)
