def from_bitarray(instr, processor):
rdm = substring(instr, 2, 0)
rn = substring(instr, 5, 3)
setflags = not processor.in_it_block()
if arch_version() < 6 and rdm == rn:
print('unpredictable')
else:
return MulT1(instr, setflags=setflags, m=rdm, d=rdm, n=rn)
def from_bitarray(instr, processor):
registers = substring(instr, 15, 0)
rn = substring(instr, 19, 16)
wback = bit_at(instr, 21)
if rn == 15 or bit_count(registers, 1, 16) < 1 or (wback and bit_at(
registers, rn) and arch_version() >= 7):
print('unpredictable')
else:
return LdmArmA1(instr, wback=wback, registers=registers, n=rn)
def from_bitarray(instr, processor):
register_list = substring(instr, 15, 0)
unaligned_allowed = False
if bit_at(register_list, 13) and arch_version() >= 7:
print('unpredictable')
else:
return PopArmA1(instr,
registers=register_list,
unaligned_allowed=unaligned_allowed)
def from_bitarray(instr, processor):
rn = substring(instr, 3, 0)
rm = substring(instr, 11, 8)
rd = substring(instr, 19, 16)
setflags = bit_at(instr, 20)
if rd == 15 or rm == 15 or rn == 15 or (rn == rd
and arch_version() < 6):
print('unpredictable')
else:
return MulA1(instr, setflags=setflags, m=rm, d=rd, n=rn)
def from_bitarray(instr, processor):
register_list = substring(instr, 15, 0)
rn = substring(instr, 19, 16)
increment = bit_at(instr, 23)
word_higher = increment == bit_at(instr, 24)
wback = bit_at(instr, 21)
if rn == 15 or (wback and bit_at(register_list, rn) and arch_version() >= 7):
print('unpredictable')
else:
return LdmExceptionReturnA1(instr, increment=increment, word_higher=word_higher, wback=wback,
registers=register_list, n=rn)
def execute(self, processor):
if processor.condition_passed():
operand1 = to_signed(processor.registers.get(self.n), 32)
operand2 = to_signed(processor.registers.get(self.m), 32)
result = operand1 * operand2
f_result = to_unsigned(result, 32)
processor.registers.set(self.d, f_result)
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 31)
processor.registers.cpsr.z = 0 if result else 1
if arch_version() == 4:
processor.registers.cpsr.c = 0 # unknown
def execute(self, processor):
if processor.condition_passed():
a = set_substring(processor.registers.get(self.d_lo), 63, 32, processor.registers.get(self.d_hi))
result = processor.registers.get(self.n) * processor.registers.get(self.m) + a
processor.registers.set(self.d_hi, substring(result, 63, 32))
processor.registers.set(self.d_lo, substring(result, 31, 0))
if self.setflags:
processor.registers.cpsr.n = bit_at(result, 63)
processor.registers.cpsr.z = 0 if result else 1
if arch_version() == 4:
processor.registers.cpsr.c = 0 # unknown
processor.registers.cpsr.v = 0 # unknown
def execute(self, processor):
if processor.condition_passed():
operand1 = processor.registers.get(self.n).int
operand2 = processor.registers.get(self.m).int
result = operand1 * operand2
f_result = BitArray(int=result, length=64)[32:]
processor.registers.set(self.d, f_result)
if self.setflags:
processor.registers.cpsr.set_n(f_result[0])
processor.registers.cpsr.set_z(not f_result.any(True))
if arch_version() == 4:
processor.registers.cpsr.set_c(False) # uknown
def execute(self, processor):
if processor.condition_passed():
result = to_signed(processor.registers.get(
self.n), 32) * to_signed(processor.registers.get(self.m), 32)
f_result = to_unsigned(result, 64)
processor.registers.set(self.d_hi, substring(f_result, 63, 32))
processor.registers.set(self.d_lo, substring(f_result, 31, 0))
if self.setflags:
processor.registers.cpsr.n = bit_at(f_result, 63)
processor.registers.cpsr.z = 0 if f_result else 1
if arch_version() == 4:
processor.registers.cpsr.c = 0 # unknown
processor.registers.cpsr.v = 0 # unknown
def from_bitarray(instr, processor):
rm = substring(instr, 3, 0)
type_o = substring(instr, 6, 5)
imm5 = substring(instr, 11, 7)
rt = substring(instr, 15, 12)
rn = substring(instr, 19, 16)
add = bit_at(instr, 23)
shift_t, shift_n = decode_imm_shift(type_o, imm5)
post_index = True
if rt == 15 or rn == 15 or rn == rt or rm or (arch_version() < 6 and rm == rn):
print('unpredictable')
else:
return StrbtA2(instr, register_form=True, add=add, post_index=post_index, t=rt, n=rn, m=rm, shift_t=shift_t,
shift_n=shift_n)
def from_bitarray(instr, processor):
rm = substring(instr, 3, 0)
rt = substring(instr, 15, 12)
rn = substring(instr, 19, 16)
add = bit_at(instr, 23)
w = bit_at(instr, 21)
index = bit_at(instr, 24)
wback = (not index) or w
shift_t = SRType.LSL
shift_n = 0
if rt == 15 or rm == 15 or (wback and (rn == 15 and rn == rt)) or (arch_version() < 6 and wback and rm == rn):
print('unpredictable')
else:
return LdrsbRegisterA1(instr, add=add, wback=wback, index=index, m=rm, t=rt, n=rn, shift_t=shift_t,
shift_n=shift_n)
def from_bitarray(instr, processor):
rm = substring(instr, 3, 0)
type_o = substring(instr, 6, 5)
imm5 = substring(instr, 11, 7)
rt = substring(instr, 15, 12)
rn = substring(instr, 19, 16)
index = bit_at(instr, 24)
add = bit_at(instr, 23)
w = bit_at(instr, 21)
wback = (not index) or w
shift_t, shift_n = decode_imm_shift(type_o, imm5)
if rm == 15 or (wback and (rn == 15 or rn == rt)) or (arch_version() < 6 and wback and rm == rn):
print('unpredictable')
else:
return StrRegisterA1(instr, add=add, wback=wback, index=index, m=rm, t=rt, n=rn, shift_t=shift_t,
shift_n=shift_n)
def from_bitarray(instr, processor):
rn = substring(instr, 3, 0)
rm = substring(instr, 11, 8)
rd_lo = substring(instr, 15, 12)
rd_hi = substring(instr, 19, 16)
setflags = bit_at(instr, 20)
if rd_hi == 15 or rm == 15 or rn == 15 or rd_lo == 15 or (
rd_lo == rd_hi) or (arch_version() < 6 and
(rd_hi == rn or rd_lo == rn)):
print('unpredictable')
else:
return UmullA1(instr,
setflags=setflags,
m=rm,
d_hi=rd_hi,
d_lo=rd_lo,
n=rn)
def from_bitarray(instr, processor):
w = bit_at(instr, 21)
index = bit_at(instr, 24)
rm = substring(instr, 3, 0)
rt = substring(instr, 15, 12)
rn = substring(instr, 19, 16)
add = bit_at(instr, 23)
t2 = rt + 1
wback = (not index) or w
if bit_at(rt, 0) or (not index and w) or (
t2 == 15 or rm == 15 or rm == rt or rm
== t2) or (wback and (rn == 15 or rn == rt or rn == t2)) or (
arch_version() < 6 and wback and rm == rn):
print('unpredictable')
else:
return LdrdRegisterA1(instr,
add=add,
wback=wback,
index=index,
m=rm,
t=rt,
t2=t2,
n=rn)
