def amplitude_to_ram(self, amplitude: TList(TFloat), ram: TList(TInt32)):
"""Convert amplitude values to RAM profile data.
To be used with :const:`RAM_DEST_ASF`.
:param amplitude: List of amplitude values in units of full scale.
:param ram: List to write RAM data into.
Suitable for :meth:`write_ram`.
"""
for i in range(len(ram)):
ram[i] = self.amplitude_to_asf(amplitude[i]) << 18
def frequency_to_ram(self, frequency: TList(TFloat), ram: TList(TInt32)):
"""Convert frequency values to RAM profile data.
To be used with :const:`RAM_DEST_FTW`.
:param frequency: List of frequency values in Hz.
:param ram: List to write RAM data into.
Suitable for :meth:`write_ram`.
"""
for i in range(len(ram)):
ram[i] = self.frequency_to_ftw(frequency[i])
def turns_to_ram(self, turns: TList(TFloat), ram: TList(TInt32)):
"""Convert phase values to RAM profile data.
To be used with :const:`RAM_DEST_POW`.
:param turns: List of phase values in turns.
:param ram: List to write RAM data into.
Suitable for :meth:`write_ram`.
"""
for i in range(len(ram)):
ram[i] = self.turns_to_pow(turns[i]) << 16
def turns_amplitude_to_ram(self, turns: TList(TFloat),
amplitude: TList(TFloat), ram: TList(TInt32)):
"""Convert phase and amplitude values to RAM profile data.
To be used with :const:`RAM_DEST_POWASF`.
:param turns: List of phase values in turns.
:param amplitude: List of amplitude values in units of full scale.
:param ram: List to write RAM data into.
Suitable for :meth:`write_ram`.
"""
for i in range(len(ram)):
ram[i] = ((self.turns_to_pow(turns[i]) << 16) |
self.amplitude_to_asf(amplitude[i]) << 2)
def patterns_to_reg(patterns: TList(TInt32)) -> TInt32:
data = 0
assert len(patterns) <= 4
for i in range(len(patterns)):
data |= (patterns[i] & 0xf) << (4 * i)
data |= 1 << (16 + i)
return data
def read_ram(self, data: TList(TInt32)):
"""Read data from RAM.
The profile to read from and the step, start, and end address
need to be configured before and separately using
:meth:`set_profile_ram` and the parent CPLD `set_profile`.
:param data: List to be filled with data read from RAM.
"""
self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
self.chip_select)
self.bus.write((_AD9910_REG_RAM | 0x80) << 24)
n = len(data) - 1
if n > 0:
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_INPUT, 32,
urukul.SPIT_DDS_RD, self.chip_select)
preload = min(n, 8)
for i in range(n):
self.bus.write(0)
if i >= preload:
data[i - preload] = self.bus.read()
self.bus.set_config_mu(
urukul.SPI_CONFIG | spi.SPI_INPUT | spi.SPI_END, 32,
urukul.SPIT_DDS_RD, self.chip_select)
self.bus.write(0)
for i in range(preload + 1):
data[(n - preload) + i] = self.bus.read()
def program_rpc(self, program, channels=None) -> TList(TBytes):
"""
Wrapper for :meth:`program_host` with only one return value for use in RPCs
:param program: (list) Wavesynth program.
:param channels: (list[int]) Channel indices to use. If unspecified, all
channels are used.
"""
_, channel_data_list = self.program_host(program, channels)
return channel_data_list
def set_group_mu(self, dac: TInt32, data: TList(TInt32)):
"""Write a group of DAC channels in machine units.
:param dac: First channel in DAC channel group (0-31). The `log2_width`
LSBs must be zero.
:param data: List of DAC data pairs (2x16 bit unsigned) to write,
in machine units. Data exceeding group size is ignored.
If the list length is less than group size, the remaining
DAC channels within the group are cleared to 0 (machine units).
"""
if dac & (self.width - 1):
raise ValueError("Group index LSBs must be zero")
rtio_output_wide(self.channel | dac, data)
def write_ram(self, data: TList(TInt32)):
"""Write data to RAM.
The profile to write to and the step, start, and end address
need to be configured before and separately using
:meth:`set_profile_ram` and the parent CPLD `set_profile`.
:param data: Data to be written to RAM.
"""
self.bus.set_config_mu(urukul.SPI_CONFIG, 8, urukul.SPIT_DDS_WR,
self.chip_select)
self.bus.write(_AD9910_REG_RAM << 24)
self.bus.set_config_mu(urukul.SPI_CONFIG, 32,
urukul.SPIT_DDS_WR, self.chip_select)
for i in range(len(data) - 1):
self.bus.write(data[i])
self.bus.set_config_mu(urukul.SPI_CONFIG | spi.SPI_END, 32,
urukul.SPIT_DDS_WR, self.chip_select)
self.bus.write(data[len(data) - 1])
def rtio_output_wide(target: TInt32, data: TList(TInt32)) -> TNone:
raise NotImplementedError("syscall not simulated")
def rtio_output_wide(time_mu: TInt64, channel: TInt32, addr: TInt32,
data: TList(TInt32)) -> TNone:
raise NotImplementedError("syscall not simulated")