def __port_set_value__(self, port: Port, value: str):
if (port.port_type + "_port") in Port.rule_conditions:
port.add_rule(
(port.port_type + "_port"), "set_value({})".format(value)
)
else:
port.add_rule("source_present", "set_value({})".format(value))
port.remove_condition("both_present")
if port.direction == "in":
port.in_entity = False
def __init__(self):
super().__init__(self.INTERFACE_TYPE_NAME)
self.add_port(Port("strobe"))
self.add_port(
Port(
"data",
data_type="std_logic_vector",
data_width=Port.DataWidth("DATA_WIDTH - 1", "downto", 0),
)
)
self.add_port(Port("data_error", optional=True))
self.add_port(Port("stall", direction="out", optional=True))
self.add_port(Port("vsync", optional=True))
vcomplete = Port("vcomplete", optional=True)
vcomplete.add_rule("sink_missing", "fallback_port(vsync)", False)
vcomplete.add_rule(
"sink_missing", "fallback_port(data_unit_complete)", False
)
self.add_port(vcomplete)
hcomplete = Port("hcomplete", optional=True)
self.add_port(Port("hsync", optional=True))
hcomplete.add_rule("sink_missing", "fallback_port(hsync)", False)
self.add_port(hcomplete)
self.add_port(Port("xres", data_type="std_logic_vector", optional=True))
self.add_port(Port("yres", data_type="std_logic_vector", optional=True))
self.add_port(Port("data_unit_complete", optional=True))
